clang-format: re-format for clang-18

clang-format-18 isn't compatible with the clang-format-17 output, so we
need to reformat the code with the latest version. The way clang-18
handles lambda forma

clang-format: re-format for clang-18

clang-format-18 isn't compatible with the clang-format-17 output, so we
need to reformat the code with the latest version. The way clang-18
handles lambda formatting also changed, so we have made changes to the
organization default style format to better handle lambda formatting.

See I5e08687e696dd240402a2780158664b7113def0e for updated style.
See Iea0776aaa7edd483fa395e23de25ebf5a6288f71 for clang-18 enablement.

Change-Id: I1210c7b95e65a82cc5675ada03441af6727a3930
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>

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cpuinfoapp: Make PECI features optional

Add a feature flag `cpuinfo-peci` to optionally disable the features in
cpuinfoapp that rely on PECI (PPIN, SST), to support configurations that
want I2C-base

cpuinfoapp: Make PECI features optional

Add a feature flag `cpuinfo-peci` to optionally disable the features in
cpuinfoapp that rely on PECI (PPIN, SST), to support configurations that
want I2C-based SSPEC detection but don't want to use libpeci.

Tested: Disabled `cpuinfo-peci` and verified SSPEC was still written
into the Model property.

Change-Id: Ie3ab9214d9d6ab238a61933de3e3856eca298fa8
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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clang-format: copy latest and re-format

clang-format-16 has some backwards incompatible changes that require
additional settings for best compatibility and re-running the formatter.
Copy the latest

clang-format: copy latest and re-format

clang-format-16 has some backwards incompatible changes that require
additional settings for best compatibility and re-running the formatter.
Copy the latest .clang-format from the docs repository and reformat the
repository.

Change-Id: I172b14c1a881c734851b7dc6e0e90ee2e11cce03
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>

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Update to the new sdbusplus namespace format

The sdbusplus namespace format was updated in [1]. This updates the
local namespaces to the new format.

[1]: https://github.com/openbmc/sdbusplus/commit

Update to the new sdbusplus namespace format

The sdbusplus namespace format was updated in [1]. This updates the
local namespaces to the new format.

[1]: https://github.com/openbmc/sdbusplus/commit/5011340e14da7fc04f8b20721c4631f778200edd

Change-Id: Ic6b874fb86d2ff2192d8067871bd2170696f2b8c
Signed-off-by: Jason M. Bills <jason.m.bills@intel.com>

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sdbusplus: use shorter type aliases

The sdbusplus headers provide shortened aliases for many types.
Switch to using them to provide better code clarity and shorter
lines. Possible replacements are

sdbusplus: use shorter type aliases

The sdbusplus headers provide shortened aliases for many types.
Switch to using them to provide better code clarity and shorter
lines. Possible replacements are for:
* bus_t
* exception_t
* manager_t
* match_t
* message_t
* object_t
* slot_t

Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Change-Id: Ibc88a5de1e7a11d332410985f29698b24aeae983

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Move PPIN to UniqueIdentifier

The PPIN should be published in Redfish as the
ProtectedIdentificationNumber property rather than SerialNumber. So we
will publish the new UniqueIdentifier D-Bus interf

Move PPIN to UniqueIdentifier

The PPIN should be published in Redfish as the
ProtectedIdentificationNumber property rather than SerialNumber. So we
will publish the new UniqueIdentifier D-Bus interface from cpuinfoapp,
rather than modifying the Asset interface served by smbios-mdrv2.

Tested:
Wait for BIOS to finish and check D-Bus property:
$ busctl get-property xyz.openbmc_project.CPUInfo \
/xyz/openbmc_project/inventory/system/chassis/motherboard/cpu0 \
xyz.openbmc_project.Inventory.Decorator.UniqueIdentifier \
UniqueIdentifier
s "8a8b34a8abcd76a"

Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
Change-Id: Ib65f373f3b7a253a458701d9faf10cdb4cddbb07

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Retry PIROM reads to workaround possible failures

PIROM is supposed to be reliable and available in all power states, but
some CPUs have bugs which can cause reads to return invalid data in some
sma

Retry PIROM reads to workaround possible failures

PIROM is supposed to be reliable and available in all power states, but
some CPUs have bugs which can cause reads to return invalid data in some
small time windows. The root causes are complicated, so although the BMC
could technically detect these windows it would take a lot of work.
Instead, this commit just adds logic to read the SSpec from PIROM
multiple times and consider it a success when two reads return the same
data. This relies on the reasonable assumption that the corrupted data
will most likely not look like a valid SSpec, and that it's very
unlikely to hit the invalid window multiple times.

This code still only modifies two D-Bus properties, but now those values
are determined at (potentially) different times, so the property setting
functions are rewritten to work with a global property list. As the
property values are determined, they are added to the list, and are
re-processed as needed (e.g. object/interface gets readded).

Tested: (On 1-CPU platform without working PIROM interface)
- Modified readSSpec to return spoofed value, AC cycled and verified
it was set on target object/interface. Also warm reset host (which
reinitializes D-Bus objects due to SMBIOS tables being resent), and
verified properties are set again.
- Restarted target service (smbios-mdrv2) and verified this service
restarts and re-sets all target properties.

Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
Change-Id: I963a2c145f1b97b05046da795af97bd7028bc807

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Defer PPIN read until BIOS enables it

On platforms with AST2600 BMC, we now boot fast enough to read the PPIN
over PECI before the BIOS has a chance to enable it (by default it is
not readable). Thi

Defer PPIN read until BIOS enables it

On platforms with AST2600 BMC, we now boot fast enough to read the PPIN
over PECI before the BIOS has a chance to enable it (by default it is
not readable). This commit delays the RdPkgConfig until BIOS is done
with POST.

Without this change, a value of 0 is read (and 0x90 CC - but that's
ignored), which causes us to drop it.

This also removes some unnecessary phosphor namespacing.

Tested:
- Booted from AC cycle, confirmed from journal logs that cpuinfoapp
delays an extra minute before running through getProcessorInfo. PPIN
is now set into SerialNumber D-Bus property and shown on Redfish.

Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
Change-Id: Ie3e8c668c6b24b42ced22fd9e103d1518702d78a

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Get i2c addresses from configuration files.

Different platforms have different bus topology.
Use the peci address and i2c address specified in
json file to read data from cpu.

Tested:
Update basebo

Get i2c addresses from configuration files.

Different platforms have different bus topology.
Use the peci address and i2c address specified in
json file to read data from cpu.

Tested:
Update baseboard json file:
{
"Address": "0x30",
"Bus": 0,
"CpuID": 1,
"Name": "CPU 1",
"PresenceGpio": [
{
"Name": "CPU1_PRESENCE",
"Polarity": "Low"
}
],
"PiromI2cBus": 13,
"PiromI2cAddress": "0x50",
"Type": "XeonCPU"
}
Verified that correct bus addresses are used.

Signed-off-by: Zhikui Ren <zhikui.ren@intel.com>
Change-Id: Ib133958af8349b43c2f8f73c32d1aaa0d5bf52eb

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cpuinfoapp: Add SST discovery feature

Retrieve Intel Speed Select Technology (SST) configuration values for
all CPUs via PECI (OS-PCode mailbox). Each CPU may have up to three
Performance Profiles (

cpuinfoapp: Add SST discovery feature

Retrieve Intel Speed Select Technology (SST) configuration values for
all CPUs via PECI (OS-PCode mailbox). Each CPU may have up to three
Performance Profiles (PP), each with accompanying Base Frequency (BF)
information.

Discovery is started immediately, but if no CPUs are found or any
unexpected PECI error is encountered, discovery is aborted and scheduled
for periodic retries until complete.

The profile data is published on D-Bus using two predefined interfaces:
- xyz.openbmc_project.Control.Processor.CurrentOperationConfig, which
is implemented on each "cpu" object in the inventory, and contains
mutable properties for OOB configuration (modifiying properties not
supported yet).
- xyz.openbmc_project.Inventory.Item.Cpu.OperationConfig, which is
implemented on separate "config" objects and contains the readonly
properties for each performance profile.

Tested:
- Profiled performance of PECI operations via code instrumentation
(takes ~2 min per CPU on ast2500 during BMC boot, ~2 sec during BMC idle).
- Validated Redfish output against Linux driver using included python
tool.
- Injected PECI failures in code to test error handling, and tested
with Linux OS idling on host to make sure WOP is working.

Change-Id: I0d8ae79655dfd2880cf3bae6abe600597740df7c
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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Move downstream package to upstream

Use upstream cpu interface

Signed-off-by: Zhikui Ren <zhikui.ren@intel.com>
Change-Id: I490482b212df4b73cbdedaba0bc5fefa229a5489