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Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0, v8.0.0, v7.2.0, v7.0.0, v6.2.0, v6.1.0, v5.2.0, v5.0.0, v4.2.0 |
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293c76cb |
| 21-May-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging
target/xtensa: SR reorganization and options for modern cores
Reorganize special register handling to support configu
Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging
target/xtensa: SR reorganization and options for modern cores
Reorganize special register handling to support configurations with
conflicting SR definitions.
Implement options used by the modern xtensa cores:
- memory protection unit;
- block prefetch;
- exclusive access
Add special register definitions and IRQ types for ECC/parity,
gather/scatter and IDMA.
# gpg: Signature made Mon 20 May 2019 18:53:05 BST
# gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg: issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044
* remotes/xtensa/tags/20190520-xtensa:
target/xtensa: implement exclusive access option
target/xtensa: update list of exception causes
target/xtensa: implement block prefetch option opcodes
target/xtensa: implement DIWBUI.P opcode
target/xtensa: implement MPU option
target/xtensa: add parity/ECC option SRs
target/xtensa: define IDMA and gather/scatter IRQ types
target/xtensa: make internal MMU functions static
target/xtensa: get rid of centralized SR properties
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
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Revision tags: v4.0.0 |
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b345e140 |
| 18-Apr-2019 |
Max Filippov <jcmvbkbc@gmail.com> |
target/xtensa: implement exclusive access option
The Exclusive Instructions provide a general-purpose mechanism for
atomic updates of memory-based synchronization variables that can be
used for excl
target/xtensa: implement exclusive access option
The Exclusive Instructions provide a general-purpose mechanism for
atomic updates of memory-based synchronization variables that can be
used for exclusion algorithms.
Use cmpxchg-based implementation that is sufficient for the typical use
of exclusive access in atomic operations.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
show more ...
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