Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into staging

target/xtensa updates for 5.2:

- add NMI support;
- add DFPU option implementation;
- update FPU tests to support bot

Merge remote-tracking branch 'remotes/xtensa/tags/20200821-xtensa' into staging

target/xtensa updates for 5.2:

- add NMI support;
- add DFPU option implementation;
- update FPU tests to support both FPU2000 and DFPU;
- add example cores with FPU2000 and DFPU.

# gpg: Signature made Fri 21 Aug 2020 21:09:37 BST
# gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg: issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20200821-xtensa: (24 commits)
target/xtensa: import DSP3400 core
target/xtensa: import de233_fpu core
tests/tcg/xtensa: add DFP0 arithmetic tests
tests/tcg/xtensa: test double precision load/store
tests/tcg/xtensa: add fp0 div and sqrt tests
tests/tcg/xtensa: update test_lsc for DFPU
tests/tcg/xtensa: update test_fp1 for DFPU
tests/tcg/xtensa: update test_fp0_conv for DFPU
tests/tcg/xtensa: expand madd tests
tests/tcg/xtensa: update test_fp0_arith for DFPU
tests/tcg/xtensa: fix test execution on ISS
target/xtensa: implement FPU division and square root
target/xtensa: add DFPU registers and opcodes
target/xtensa: add DFPU option
target/xtensa: don't access BR regfile directly
target/xtensa: move FSR/FCR register accessors
target/xtensa: rename FPU2000 translators and helpers
target/xtensa: support copying registers up to 64 bits wide
target/xtensa: add geometry to xtensa_get_regfile_by_name
softfloat: add xtensa specialization for pickNaNMulAdd
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tests/tcg/xtensa: fix test execution on ISS

Space for test results may be allocated in IRAM which is only
word-accessible. Use full 32-bit words to access test results.

Signed-off-by: Max Filippov

tests/tcg/xtensa: fix test execution on ISS

Space for test results may be allocated in IRAM which is only
word-accessible. Use full 32-bit words to access test results.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging

target/xtensa: FLIX support, various fixes and test improvements

- add FLIX (flexible length instructions extension)

Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging

target/xtensa: FLIX support, various fixes and test improvements

- add FLIX (flexible length instructions extension) support;
- make testsuite runnable on wider range of xtensa cores;
- add floating point opcode tests;
- don't add duplicate 'static' in import_core.sh script;
- fix undefined opcodes detection in test_mmuhifi_c3 overlay.

# gpg: Signature made Thu 28 Feb 2019 12:53:23 GMT
# gpg: using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg: issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20190228-xtensa: (40 commits)
tests/tcg/xtensa: add FPU2000 coprocessor tests
tests/tcg/xtensa: add FP1 group tests
tests/tcg/xtensa: add FP0 group conversion tests
tests/tcg/xtensa: add FP0 group arithmetic tests
tests/tcg/xtensa: add LSCI/LSCX group tests
tests/tcg/xtensa: add test for FLIX
tests/tcg/xtensa: conditionalize MMU-related tests
tests/tcg/xtensa: conditionalize windowed register tests
tests/tcg/xtensa: conditionalize and fix s32c1i tests
tests/tcg/xtensa: fix SR tests for big endian configs
tests/tcg/xtensa: conditionalize and expand SR tests
tests/tcg/xtensa: conditionalize timer/CCOUNT tests
tests/tcg/xtensa: conditionalize interrupt tests
tests/tcg/xtensa: add straightforward conditionals
tests/tcg/xtensa: conditionalize cache option tests
tests/tcg/xtensa: conditionalize debug option tests
tests/tcg/xtensa: enable boolean tests
tests/tcg/xtensa: fix endianness issues in test_b
tests/tcg/xtensa: don't use optional opcodes in generic code
tests/tcg/xtensa: support configs with LITBASE
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

tests/tcg/xtensa: add FP0 group arithmetic tests

Test arithmetic operations for normal, NaN and Inf arguments.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

tests/tcg/xtensa: conditionalize interrupt tests

Make interrupt tests conditional on the presence of interrupt option and
on the presence of level-1 and high level software interrupts. Don't use
har

tests/tcg/xtensa: conditionalize interrupt tests

Make interrupt tests conditional on the presence of interrupt option and
on the presence of level-1 and high level software interrupts. Don't use
hard-coded interrupt level for the high level interrupt tests, choose
high level software IRQ and use its configured level.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

tests/tcg/xtensa: conditionalize debug option tests

Make debug tests conditional on the presence of the debug option in the
config and tests that depend on the presence/number of instruction or
data

tests/tcg/xtensa: conditionalize debug option tests

Make debug tests conditional on the presence of the debug option in the
config and tests that depend on the presence/number of instruction or
data breakpoint registers on the corresponding definitions. Use
configured debug interrupt level instead of the hardcoded value to set
up IRQ handler and access debug EPC register.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

tests/tcg/xtensa: don't use optional opcodes in generic code

Don't use 'loop' opcode in generic testsuite completion code, only use
core opcodes to make it work with any configuration.

Signed-off-b

tests/tcg/xtensa: don't use optional opcodes in generic code

Don't use 'loop' opcode in generic testsuite completion code, only use
core opcodes to make it work with any configuration.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

tests/tcg/xtensa: indicate failed tests

When test suite with multiple tests fails it's not obvious which test
failed. Pring "failed" in every invocation of test_fail. Do printing
when DEBUG preproce

tests/tcg/xtensa: indicate failed tests

When test suite with multiple tests fails it's not obvious which test
failed. Pring "failed" in every invocation of test_fail. Do printing
when DEBUG preprocessor macro is defined.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

Merge remote-tracking branch 'remotes/xtensa/tags/20140224-xtensa' into staging

Xtensa fixes and improvements queue 2014-02-24:
- add support for ML605 and KC705 FPGA boards;
- flush opencores_eth q

Merge remote-tracking branch 'remotes/xtensa/tags/20140224-xtensa' into staging

Xtensa fixes and improvements queue 2014-02-24:
- add support for ML605 and KC705 FPGA boards;
- flush opencores_eth queue when new RX descriptor is available;
- add basic checks to cache opcodes;
- make core configuration available to tests;
- implement HW config ID special registers.

# gpg: Signature made Mon 24 Feb 2014 00:52:42 GMT using RSA key ID F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg: aka "Max Filippov <jcmvbkbc@gmail.com>"

* remotes/xtensa/tags/20140224-xtensa:
target-xtensa: provide HW confg ID registers
target-xtensa: refactor standard core configuration
target-xtensa: add basic tests for cache opcodes
target-xtensa: allow using core configuration in tests
target-xtensa: add overridable test_init macro
target-xtensa: add basic checks to icache opcodes
target-xtensa: add basic checks to dcache opcodes
target-xtensa: add RRRI4 opcode format fields
opencores_eth: flush queue whenever can_receive can go from false to true
hw/xtensa: add support for ML605 and KC705 FPGA board

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target-xtensa: allow using core configuration in tests

Add path to the core configuration directory to test build command and
replace .include asm directive with #include to enable preprocessing.

S

target-xtensa: allow using core configuration in tests

Add path to the core configuration directory to test build command and
replace .include asm directive with #include to enable preprocessing.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

target-xtensa: add overridable test_init macro

Some test suites, like MMU, need per-test initialization. Don't make them
redefine test macro, add test_init for that purpose.

Signed-off-by: Max Fili

target-xtensa: add overridable test_init macro

Some test suites, like MMU, need per-test initialization. Don't make them
redefine test macro, add test_init for that purpose.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

Merge branch 'master' of git://git.qemu.org/qemu into prep-up

Conflicts:
hw/Makefile.objs
hw/ppc_prep.c

Signed-off-by: Andreas Färber <andreas.faerber@web.de>

target-xtensa: add SR accessibility unit tests

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

Merge branch 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensa

* 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensa:
target-xtensa: Start QOM'ifying CPU init
target-xtensa: QOM'ify CPU reset

Merge branch 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensa

* 'xtensa' of git://jcmvbkbc.spb.ru/dumb/qemu-xtensa:
target-xtensa: Start QOM'ifying CPU init
target-xtensa: QOM'ify CPU reset
target-xtensa: QOM'ify CPU
target-xtensa: improve unit tests debugging
target-xtensa: Move helpers.h to helper.h

show more ...

target-xtensa: improve unit tests debugging

- add testcase announcement;
- add global symbols for individual tests;
- add host-debug-* makefile target.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.c

target-xtensa: improve unit tests debugging

- add testcase announcement;
- add global symbols for individual tests;
- add host-debug-* makefile target.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

show more ...

tests: mv tests/* -> tests/tcg

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>