Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0 |
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#
d316f1b1 |
| 28-Feb-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-maintainer-updates-280224-1' of https://gitlab.com/stsquad/qemu into staging
Testing, gdbstub and plugin updates:
- fix some test/tcg license headers to GPLv2+ - bump up check-t
Merge tag 'pull-maintainer-updates-280224-1' of https://gitlab.com/stsquad/qemu into staging
Testing, gdbstub and plugin updates:
- fix some test/tcg license headers to GPLv2+ - bump up check-tcg timeout to 120s - avoid re-building VM images too often - update OpenBSD to 7.4 - use GDBFeature to build gdbstub XML - unify plugin vcpu count under qemu_plugin_num_vcpus - avoid spurious idle/resume callbacks on new vCPUs - ensure nios2-linux-user processes async work - call vcpu_init plugin callback through async work - define plugin helpers when registers being read - add plugin API for reading register values - add support for register tracking to execlog - update plugin docs with assumptions - mention plugins can trigger tb_flush in mttcg design doc
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmXfAv0ACgkQ+9DbCVqe # KkQyogf/X6T5lWsdZGb22FOYzaTLf5gfCPXArIVN+GsjSae3dU6qy/qVM1VRJQPw # mH8kvMY7QO5V9M2tL33WtZZg6hqWypXYU+Hit6sMmveKYMKS9ESEX28x3yybgt8Y # fyDywNODX7bs8Wb6NQjVkZvTmM2llrHEtQXPffaXaPyxOAzlGTV9Mf3Sop9rk4nG # 8IchzLmOOQ7XnVst/KRyq+29oOYsbyUtj13tNeWBZ5iXFDT6Q/nGwPQ12U2Ztn9N # FZvyzGG707dFaEDxIr4pl7n+lHJto29LMlSXlocANwG6wFNP3nfkSw/dXw3nkZZK # pOfrQKvnnunJKBd7495LYZxTDe505Q== # =/k97 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 28 Feb 2024 09:55:09 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* tag 'pull-maintainer-updates-280224-1' of https://gitlab.com/stsquad/qemu: (29 commits) docs/devel: plugins can trigger a tb flush docs/devel: document some plugin assumptions docs/devel: lift example and plugin API sections up contrib/plugins: extend execlog to track register changes contrib/plugins: fix imatch tests/tcg: expand insn test case to exercise register API plugins: add an API to read registers plugins: create CPUPluginState and migrate plugin_mask gdbstub: expose api to find registers plugins: Use different helpers when reading registers cpu: call plugin init hook asynchronously linux-user: ensure nios2 processes queued work plugins: fix order of init/idle/resume callback plugins: add qemu_plugin_num_vcpus function plugins: remove previous n_vcpus functions from API gdbstub: Add members to identify registers to GDBFeature hw/core/cpu: Remove gdb_get_dynamic_xml member gdbstub: Infer number of core registers from XML gdbstub: Simplify XML lookup gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
542b10bd |
| 27-Feb-2024 |
Alex Bennée <alex.bennee@linaro.org> |
tests/tcg: update licenses to GPLv2 as intended
My default header template is GPLv3 but for QEMU code we really should stick to GPLv2-or-later (allowing others to up-license it if they wish). While
tests/tcg: update licenses to GPLv2 as intended
My default header template is GPLv3 but for QEMU code we really should stick to GPLv2-or-later (allowing others to up-license it if they wish). While this is test code we should still be consistent on the source distribution.
I wrote all of this code so its not a problem. However there remains one GPLv3 file left which is the crt0-tc2x.S for TriCore.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-2-alex.bennee@linaro.org>
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#
0b58dc45 |
| 25-Jul-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
trivial-patches 25-07-2023
# -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmS/2vgPHG1
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
trivial-patches 25-07-2023
# -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmS/2vgPHG1qdEB0bHMu # bXNrLnJ1AAoJEHAbT2saaT5ZT6MH/j5L3P9yLV6TqW+DkhCppbmBygqxz2SbQjwl # dVVfSLpJNbtpvLfEnvpb+ms+ZdaOCGj8IofAVf9w0VaIYJFP1srFphY/1x+RYVnw # kDjCLzuLNSCAdCV2HPqsrMKzdFctZ/MfK+QzfcGik9IvmCNPYWOhpmevs+xAIEJd # b0xk152zy2fIIC3vKK+3KcM7MFkqZWJ6z0pzUZAyEBS+aQyuZNPJ/cO8xMXotbP2 # jqv12SNGV2GLH1acvsd8GQwDB9MamstB4r8NWpSpT/AyPwOgmMR+j5B8a/WEBJCs # OcEW/pEyrumSygqf9z01YoNJQUCSvSpg5aq4+S2cRDslmUgFDmw= # =wCoQ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 25 Jul 2023 15:23:52 BST # gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59 # gpg: issuer "mjt@tls.msk.ru" # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full] # gpg: aka "Michael Tokarev <mjt@debian.org>" [full] # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59
* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: qapi: Correct "eg." to "e.g." in documentation hw/pci: add comment to explain checking for available function 0 in pci hotplug target/tricore: Rename tricore_feature hw/9pfs: spelling fixes other architectures: spelling fixes arm: spelling fixes s390x: spelling fixes migration: spelling fixes
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
8b81968c |
| 14-Jul-2023 |
Michael Tokarev <mjt@tls.msk.ru> |
other architectures: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.0.0, v7.2.0 |
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#
028f2361 |
| 09-Jun-2022 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-target-arm-20220609' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * target/arm: Declare support for FEAT_RASv1p1 * target/arm: Implement FEAT_D
Merge tag 'pull-target-arm-20220609' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * target/arm: Declare support for FEAT_RASv1p1 * target/arm: Implement FEAT_DoubleFault * Fix 'writeable' typos * xlnx_dp: Implement vblank interrupt * target/arm: Move page-table-walk code to ptw.c * target/arm: Preparatory patches for SME support
# -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmKht40ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3p/hEACkUlUhKStyMCimLZJQ2wfG # rBO6zHPNVDWtWqUy/1e5HgeU6HXqk0TXLGIbk+6/2y1wos2KGHPOIjIw0miPuZF9 # tsVvwjKlnOPecJc5tm3vxPswBK29Rp7BtNTIXSlGOcByOK1L94ern5pi29QK1ltm # rZ8vbzJTJ58vCTUkYjcnIeLWAWzgiEgVdEWwl7+3dGIr0x9uawfku/eFd0zFb5+v # TtBUz0d92te7SehtiGI9CbdQnxvSOLV/3LbAhPhG8G4tG5YwxW7aQbT/YnBVLqek # CiLuN9/Wib7UYkYpeP1dAGhqMmPmIxrwCuxFMXhzARiiyLSKZhBHRCOv5WF8wkL5 # F7j+Cx8v+A6wUQBx09Oxb9mK6EDcjiaaSqlDSoq4WvvUWVphugFyoypKTa8XZM8H # qrs+jOyODFeRz6QOiei2FG0eswvSDIFMZt8mtFC5vutSSzIaGmD/yCDU/oMfoFwC # r7O85dVhhDnyagmp1wnQaePSehoekcnN87A4Zego/LM6sGua+3GYMR5qnKnMsKgr # wSJ8nPHGK30et4qfCqdYH0FK2EoRwTc/17C5FXV5FiMXQuEPuyMRqrUFj8Iv4AZc # MqvNfJvDHS6ZXrZv4a9rFY/LkOfupC/Zsd+p3QoT3CTicebaxEr/6TTOR9vFvw3k # InzNe4cc9Be4TtyamRA1mA== # =a85M # -----END PGP SIGNATURE----- # gpg: Signature made Thu 09 Jun 2022 02:04:13 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
* tag 'pull-target-arm-20220609' of https://git.linaro.org/people/pmaydell/qemu-arm: (55 commits) target/arm: Add ID_AA64SMFR0_EL1 target/arm: Add isar_feature_aa64_sme target/arm: Export bfdotadd from vec_helper.c target/arm: Move expand_pred_h to vec_internal.h target/arm: Use expand_pred_b in mve_helper.c target/arm: Move expand_pred_b to vec_internal.h target/arm: Export sve contiguous ldst support functions target/arm: Split out load/store primitives to sve_ldst_internal.h target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el target/arm: Use uint32_t instead of bitmap for sve vq's target/arm: Merge aarch64_sve_zcr_get_valid_len into caller target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset target/arm: Hoist arm_is_el2_enabled check in sve_exception_el target/arm: Use el_is_in_host for sve_exception_el target/arm: Use el_is_in_host for sve_zcr_len_for_el target/arm: Add el_is_in_host target/arm: Remove fp checks from sve_exception_el target/arm: Remove route_to_el2 check from sve_exception_el linux-user/aarch64: Introduce sve_vq target/arm: Rename TBFLAG_A64 ZCR_LEN to VL ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
9323e79f |
| 08-Jun-2022 |
Peter Maydell <peter.maydell@linaro.org> |
Fix 'writeable' typos
We have about 30 instances of the typo/variant spelling 'writeable', and over 500 of the more common 'writable'. Standardize on the latter.
Change produced with:
sed -i -e
Fix 'writeable' typos
We have about 30 instances of the typo/variant spelling 'writeable', and over 500 of the more common 'writable'. Standardize on the latter.
Change produced with:
sed -i -e 's/\([Ww][Rr][Ii][Tt]\)[Ee]\([Aa][Bb][Ll][Ee]\)/\1\2/g' $(git grep -il writeable)
and then hand-undoing the instance in linux-headers/linux/kvm.h.
Most of these changes are in comments or documentation; the exceptions are: * a local variable in accel/hvf/hvf-accel-ops.c * a local variable in accel/kvm/kvm-all.c * the PMCR_WRITABLE_MASK macro in target/arm/internals.h * the EPT_VIOLATION_GPA_WRITABLE macro in target/i386/hvf/vmcs.h (which is never used anywhere) * the AR_TYPE_WRITABLE_MASK macro in target/i386/hvf/vmx.h (which is never used anywhere)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-id: 20220505095015.2714666-1-peter.maydell@linaro.org
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Revision tags: v7.0.0, v6.2.0, v6.1.0 |
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#
8814b132 |
| 18-Jan-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-180121-2' into staging
Testing, gdbstub and semihosting patches:
- clean-ups to docker images - drop duplicate jobs from
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-180121-2' into staging
Testing, gdbstub and semihosting patches:
- clean-ups to docker images - drop duplicate jobs from shippable - prettier tag generation (+gtags) - generate browsable source tree - more Travis->GitLab migrations - fix checkpatch to deal with commits - gate gdbstub tests on 8.3.1, expand tests - support Xfer:auxv:read gdb packet - better gdbstub cleanup - use GDB's SVE register layout - make arm-compat-semihosting common - add riscv semihosting support - add HEAPINFO, ELAPSED, TICKFREQ, TMPNAM and ISERROR to semihosting
# gpg: Signature made Mon 18 Jan 2021 10:09:11 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* remotes/stsquad/tags/pull-testing-and-misc-180121-2: (30 commits) semihosting: Implement SYS_ISERROR semihosting: Implement SYS_TMPNAM semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ riscv: Add semihosting support for user mode riscv: Add semihosting support semihosting: Support SYS_HEAPINFO when env->boot_info is not set semihosting: Change internal common-semi interfaces to use CPUState * semihosting: Change common-semi API to be architecture-independent semihosting: Move ARM semihosting code to shared directories target/arm: use official org.gnu.gdb.aarch64.sve layout for registers gdbstub: ensure we clean-up when terminated gdbstub: drop gdbserver_cleanup in favour of gdb_exit gdbstub: drop CPUEnv from gdb_exit() gdbstub: add support to Xfer:auxv:read: packet gdbstub: implement a softmmu based test Revert "tests/tcg/multiarch/Makefile.target: Disable run-gdbstub-sha1 test" configure: gate our use of GDB to 8.3.1 or above test/guest-debug: echo QEMU command as well scripts/checkpatch.pl: fix git-show invocation to include diffstat gitlab: migrate the minimal tools and unit tests from Travis ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts: # default-configs/targets/riscv32-linux-user.mak # default-configs/targets/riscv64-linux-user.mak
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#
c00506aa |
| 08-Jan-2021 |
Alex Bennée <alex.bennee@linaro.org> |
gdbstub: implement a softmmu based test
This adds a new tests that allows us to test softmmu only features including watchpoints. To do achieve this we need to:
- add _exit: labels to the boot co
gdbstub: implement a softmmu based test
This adds a new tests that allows us to test softmmu only features including watchpoints. To do achieve this we need to:
- add _exit: labels to the boot codes - write a memory.py test case - plumb the test case into the build system - tweak the run_test script to: - re-direct output when asked - use socket based connection for all tests - add a small pause before connection
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210108224256.2321-6-alex.bennee@linaro.org>
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Revision tags: v5.2.0, v5.0.0 |
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#
e715f7b7 |
| 07-Apr-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stsquad/tags/pull-misc-fixes-070420-1' into staging
Various fixes:
- add .github repo lockdown config - better handle missing symbols in elf-ops - protec
Merge remote-tracking branch 'remotes/stsquad/tags/pull-misc-fixes-070420-1' into staging
Various fixes:
- add .github repo lockdown config - better handle missing symbols in elf-ops - protect fcntl64 with #ifdef - remove unused macros from test - fix handling of /proc/self/maps - avoid BAD_SHIFT in x80 softfloat - properly terminate on .hex EOF - fix configure probe on windows cross build - fix %r12 guest_base initialization
# gpg: Signature made Tue 07 Apr 2020 16:31:14 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* remotes/stsquad/tags/pull-misc-fixes-070420-1: tcg/i386: Fix %r12 guest_base initialization configure: Add -Werror to PIE probe hw/core: properly terminate loading .hex on EOF record linux-user: clean-up padding on /proc/self/maps linux-user: factor out reading of /proc/self/maps softfloat: Fix BAD_SHIFT from normalizeFloatx80Subnormal gdbstub: fix compiler complaining target/xtensa: add FIXME for translation memory leak linux-user: more debug for init_guest_space tests/tcg: remove extraneous pasting macros linux-user: protect fcntl64 with an #ifdef elf-ops: bail out if we have no function symbols .github: Enable repo-lockdown bot to refuse GitHub pull requests
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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af7fc47f |
| 03-Apr-2020 |
Alex Bennée <alex.bennee@linaro.org> |
tests/tcg: remove extraneous pasting macros
We are not using them and they just get in the way.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redha
tests/tcg: remove extraneous pasting macros
We are not using them and they just get in the way.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200403191150.863-4-alex.bennee@linaro.org>
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Revision tags: v4.2.0 |
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#
fe18911a |
| 13-Jun-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-gdbstub-cputlb-120619-3' into staging
Various fixes and updates:
- editor config tweak for shell scripts - iotest updates (still
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-gdbstub-cputlb-120619-3' into staging
Various fixes and updates:
- editor config tweak for shell scripts - iotest updates (still not default for make check) - various docker updates - gcc/ubsan updates for travis - some clean-ups for tests/vm (no serial autoinstall) - semihosting fix for Coverity - fixes for cputlb in 64-on-32 cases - gdbstub re-factor + maintainership update
# gpg: Signature made Wed 12 Jun 2019 17:55:04 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* remotes/stsquad/tags/pull-testing-gdbstub-cputlb-120619-3: (40 commits) gdbstub: Implement qemu physical memory mode gdbstub: Clear unused variables in gdb_handle_packet gdbstub: Implement target halted (? pkt) with new infra gdbstub: Implement generic set/query (Q/q pkt) with new infra gdbstub: Implement v commands with new infra gdbstub: Implement step (s pkt) with new infra gdbstub: Implement file io (F pkt) with new infra gdbstub: Implement read all registers (g pkt) with new infra gdbstub: Implement write all registers (G pkt) with new infra gdbstub: Implement read memory (m pkt) with new infra gdbstub: Implement write memory (M pkt) with new infra gdbstub: Implement get register (p pkt) with new infra gdbstub: Implement set register (P pkt) with new infra gdbstub: Implement breakpoint commands (Z/z pkt) with new infra gdbstub: Implement set_thread (H pkt) with new infra gdbstub: Implement continue with signal (C pkt) with new infra gdbstub: Implement continue (c pkt) with new infra gdbstub: Implement thread_alive (T pkt) with new infra gdbstub: Implement deatch (D pkt) with new infra gdbstub: Add infrastructure to parse cmd packets ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v4.0.0, v4.0.0-rc1, v4.0.0-rc0 |
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#
db61edad |
| 06-Mar-2019 |
Alex Bennée <alex.bennee@linaro.org> |
tests/tcg/x86_64: add a PVH crt.o for x86_64 system tests
Instead of doing the full real to 64 bit dance we are attempting to leverage Xen's PVH boot spec to go from 32 bit to 64 bit.
Signed-off-by
tests/tcg/x86_64: add a PVH crt.o for x86_64 system tests
Instead of doing the full real to 64 bit dance we are attempting to leverage Xen's PVH boot spec to go from 32 bit to 64 bit.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
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