| #
dd64bcea |
| 15-Nov-2022 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-x86-20221115' of https://gitlab.com/rth7680/qemu into staging
Fix cmpxchgl writeback to rax.
Fix lahf/sahf for 64-bit
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Merge tag 'pull-x86-20221115' of https://gitlab.com/rth7680/qemu into staging
Fix cmpxchgl writeback to rax.
Fix lahf/sahf for 64-bit
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# gpg: Signature made Mon 14 Nov 2022 18:36:06 EST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-x86-20221115' of https://gitlab.com/rth7680/qemu:
target/i386: hardcode R_EAX as destination register for LAHF/SAHF
target/i386: fix cmpxchg with 32-bit register destination
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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| #
d1bb978b |
| 11-Sep-2022 |
Paolo Bonzini <pbonzini@redhat.com> |
target/i386: fix cmpxchg with 32-bit register destination
Unlike the memory case, where "the destination operand receives a write
cycle without regard to the result of the comparison", rm must not b
target/i386: fix cmpxchg with 32-bit register destination
Unlike the memory case, where "the destination operand receives a write
cycle without regard to the result of the comparison", rm must not be
touched altogether if the write fails, including not zero-extending
it on 64-bit processors. This is not how the movcond currently works,
because it is always followed by a gen_op_mov_reg_v to rm.
To fix it, introduce a new function that is similar to gen_op_mov_reg_v
but writes to a TCG temporary.
Considering that gen_extu(ot, oldv) is not needed in the memory case
either, the two cases for register and memory destinations are different
enough that one might as well fuse the two "if (mod == 3)" into one.
So do that too.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/508
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[rth: Add a test case ]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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