|
Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0 |
|
| #
3c95fd4e |
| 26-Oct-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386: implement SHA instructions
* target/i386: check CPUID_PAE to determine 36 bit processor address space
* target
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386: implement SHA instructions
* target/i386: check CPUID_PAE to determine 36 bit processor address space
* target/i386: improve validation of AVX instructions
* require Linux 4.4 for KVM
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# gpg: Signature made Thu 26 Oct 2023 02:53:50 JST
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (24 commits)
kvm: i8254: require KVM_CAP_PIT2 and KVM_CAP_PIT_STATE2
kvm: i386: require KVM_CAP_SET_IDENTITY_MAP_ADDR
kvm: i386: require KVM_CAP_ADJUST_CLOCK
kvm: i386: require KVM_CAP_MCE
kvm: i386: require KVM_CAP_SET_VCPU_EVENTS and KVM_CAP_X86_ROBUST_SINGLESTEP
kvm: i386: require KVM_CAP_XSAVE
kvm: i386: require KVM_CAP_DEBUGREGS
kvm: i386: move KVM_CAP_IRQ_ROUTING detection to kvm_arch_required_capabilities
kvm: unify listeners for PIO address space
kvm: require KVM_CAP_IOEVENTFD and KVM_CAP_IOEVENTFD_ANY_LENGTH
kvm: assume that many ioeventfds can be created
kvm: drop reference to KVM_CAP_PCI_2_3
kvm: require KVM_IRQFD for kernel irqchip
kvm: require KVM_IRQFD for kernel irqchip
kvm: require KVM_CAP_SIGNAL_MSI
kvm: require KVM_CAP_INTERNAL_ERROR_DATA
kvm: remove unnecessary stub
target/i386: check CPUID_PAE to determine 36 bit processor address space
target/i386: validate VEX.W for AVX instructions
target/i386: group common checks in the decoding phase
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
| #
48adb240 |
| 10-Oct-2023 |
Paolo Bonzini <pbonzini@redhat.com> |
tests/tcg/i386: test-avx: add test cases for SHA new instructions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
| #
f0b95ab6 |
| 18-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* kvm: enable dirty ring for arm64
* target/i386: new features
* target/i386: AVX fixes
* configure: create a python venv unc
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* kvm: enable dirty ring for arm64
* target/i386: new features
* target/i386: AVX fixes
* configure: create a python venv unconditionally
* meson: bump to 0.63.0 and move tests from configure
* meson: Pass -j option to sphinx
* drop support for Python 3.6
* fix check-python-tox
* fix "make clean" in the source directory
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# gpg: Signature made Thu 18 May 2023 04:35:32 AM PDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (68 commits)
docs/devel: update build system docs
configure: remove unnecessary check
configure: reorder option parsing code
configure: remove unnecessary mkdir
configure: do not rerun the tests with -Werror
configure: remove compiler sanity check
build: move --disable-debug-info to meson
build: move compiler version check to meson
build: move remaining compiler flag tests to meson
build: move warning flag selection to meson
build: move stack protector flag selection to meson
build: move coroutine backend selection to meson
build: move SafeStack tests to meson
build: move sanitizer tests to meson
meson: prepare move of QEMU_CFLAGS to meson
configure, meson: move --enable-modules to Meson
configure: remove pkg-config functions
build: move glib detection and workarounds to meson
meson: drop unnecessary declare_dependency()
meson: add more version numbers to the summary
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
|
| #
9e658296 |
| 10-May-2023 |
Paolo Bonzini <pbonzini@redhat.com> |
tests/tcg/i386: correct mask for VPERM2F128/VPERM2I128
The instructions also use bits 3 and 7 of their 8-byte immediate.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
Revision tags: v8.0.0, v7.2.0 |
|
| #
e52d57c8 |
| 24-Oct-2022 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386: new decoder bugfix
* target/i386: complete x86-v3 support for TCG
# -----BEGIN PGP SIGNATURE-----
#
# iQFHBAA
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386: new decoder bugfix
* target/i386: complete x86-v3 support for TCG
# -----BEGIN PGP SIGNATURE-----
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# gpg: Signature made Sat 22 Oct 2022 03:07:16 EDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
target/i386: implement FMA instructions
target/i386: implement F16C instructions
target/i386: introduce function to set rounding mode from FPCW or MXCSR bits
target/i386: decode-new: avoid out-of-bounds access to xmm_regs[-1]
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
| #
2872b0f3 |
| 19-Oct-2022 |
Paolo Bonzini <pbonzini@redhat.com> |
target/i386: implement FMA instructions
The only issue with FMA instructions is that there are _a lot_ of them (30
opcodes, each of which comes in up to 4 versions depending on VEX.W and
VEX.L; a to
target/i386: implement FMA instructions
The only issue with FMA instructions is that there are _a lot_ of them (30
opcodes, each of which comes in up to 4 versions depending on VEX.W and
VEX.L; a total of 96 possibilities). However, they can be implement with
only 6 helpers, two for scalar operations and four for packed operations.
(Scalar versions do not do any merging; they only affect the bottom 32
or 64 bits of the output operand. Therefore, there is no separate XMM
and YMM of the scalar helpers).
First, we can reduce the number of helpers to one third by passing four
operands (one output and three inputs); the reordering of which operands
go to the multiply and which go to the add is done in emit.c.
Second, the different instructions also dispatch to the same softfloat
function, so the flags for float32_muladd and float64_muladd are passed
in the helper as int arguments, with a little extra complication to
handle FMADDSUB and FMSUBADD.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
show more ...
|
| #
cf5ec664 |
| 19-Oct-2022 |
Paolo Bonzini <pbonzini@redhat.com> |
target/i386: implement F16C instructions
F16C only consists of two instructions, which are a bit peculiar
nevertheless.
First, they access only the low half of an YMM or XMM register for the
packed
target/i386: implement F16C instructions
F16C only consists of two instructions, which are a bit peculiar
nevertheless.
First, they access only the low half of an YMM or XMM register for the
packed-half operand; the exact size still depends on the VEX.L flag.
This is similar to the existing avx_movx flag, but not exactly because
avx_movx is hardcoded to affect operand 2. To this end I added a "ph"
format name; it's possible to reuse this approach for the VPMOVSX and
VPMOVZX instructions, though that would also require adding two more
formats for the low-quarter and low-eighth of an operand.
Second, VCVTPS2PH is somewhat weird because it *stores* the result of
the instruction into memory rather than loading it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
show more ...
|
| #
214a8da2 |
| 18-Oct-2022 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* configure: don't enable firmware for targets that are not built
* configure: don't use strings(1)
* scsi, target/i386: swit
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* configure: don't enable firmware for targets that are not built
* configure: don't use strings(1)
* scsi, target/i386: switch from device_legacy_reset() to device_cold_reset()
* target/i386: AVX support for TCG
* target/i386: fix SynIC SINT assertion failure on guest reset
* target/i386: Use atomic operations for pte updates and other cleanups
* tests/tcg: extend SSE tests to AVX
* virtio-scsi: send "REPORTED LUNS CHANGED" sense data upon disk hotplug events
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# gpg: Signature made Tue 18 Oct 2022 07:58:31 EDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (53 commits)
target/i386: remove old SSE decoder
target/i386: move 3DNow to the new decoder
tests/tcg: extend SSE tests to AVX
target/i386: Enable AVX cpuid bits when using TCG
target/i386: implement VLDMXCSR/VSTMXCSR
target/i386: implement XSAVE and XRSTOR of AVX registers
target/i386: reimplement 0x0f 0x28-0x2f, add AVX
target/i386: reimplement 0x0f 0x10-0x17, add AVX
target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX
target/i386: reimplement 0x0f 0x38, add AVX
target/i386: Use tcg gvec ops for pmovmskb
target/i386: reimplement 0x0f 0x3a, add AVX
target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes
target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX
target/i386: reimplement 0x0f 0x70-0x77, add AVX
target/i386: reimplement 0x0f 0x78-0x7f, add AVX
target/i386: reimplement 0x0f 0x50-0x5f, add AVX
target/i386: reimplement 0x0f 0xd8-0xdf, 0xe8-0xef, 0xf8-0xff, add AVX
target/i386: reimplement 0x0f 0x60-0x6f, add AVX
target/i386: Introduce 256-bit vector helpers
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
| #
0339ddfa |
| 20-Sep-2022 |
Paolo Bonzini <pbonzini@redhat.com> |
tests/tcg: extend SSE tests to AVX
Extracted from a patch by Paul Brook <paul@nowt.org>.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.
tests/tcg: extend SSE tests to AVX
Extracted from a patch by Paul Brook <paul@nowt.org>.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
show more ...
|
| #
1b3a3383 |
| 20-Sep-2022 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* add help option for -audio and -audiodev
* another missing memory barrier for dirty pages
* target/i386: Raise #GP on unali
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* add help option for -audio and -audiodev
* another missing memory barrier for dirty pages
* target/i386: Raise #GP on unaligned m128 accesses
* coverity fixes + improvements to components
* add MMX and 3DNow! tests
* SSE4a fixes
* target/i386: TCG translation cleanups
* update qboot submodule
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# gpg: Signature made Mon 19 Sep 2022 09:41:43 EDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (21 commits)
qboot: update to latest submodule
build: remove extra parentheses causing missing rebuilds
target/i386: introduce insn_get_addr
target/i386: REPZ and REPNZ are mutually exclusive
target/i386: fix INSERTQ implementation
target/i386: correctly mask SSE4a bit indices in register operands
audio: add help option for -audio and -audiodev
tests/tcg: remove old SSE tests
tests/tcg: refine MMX support in SSE tests
tests/tcg: i386: add MMX and 3DNow! tests
tests/tcg: i386: fix typos in 3DNow! instructions
tests: unit: add NULL-pointer check
tests: test-qga: close socket on failure to connect
tests: unit: simplify test-visitor-serialization list tests
smbios: sanitize type from external type before checking have_fields_bitmap
coverity: put NUBus under m68k component
coverity: add new RISC-V component
spapr_pci: fix leak in spapr_phb_vfio_get_loc_code
kvm: fix memory leak on failure to read stats descriptors
target/i386: Raise #GP on unaligned m128 accesses when required.
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
| #
e02907cc |
| 09-Sep-2022 |
Paolo Bonzini <pbonzini@redhat.com> |
tests/tcg: refine MMX support in SSE tests
Extend the support to memory operands, and skip MMX instructions that
were introduced in SSE times, because they are now covered in test-mmx.
Signed-off-b
tests/tcg: refine MMX support in SSE tests
Extend the support to memory operands, and skip MMX instructions that
were introduced in SSE times, because they are now covered in test-mmx.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
show more ...
|
| #
fa7ce0b0 |
| 01-Sep-2022 |
Paolo Bonzini <pbonzini@redhat.com> |
tests/tcg: i386: add MMX and 3DNow! tests
Adjust the test-avx.py generator to produce tests specifically for
MMX and 3DNow. Using a separate generator introduces some code
duplication, but is a sim
tests/tcg: i386: add MMX and 3DNow! tests
Adjust the test-avx.py generator to produce tests specifically for
MMX and 3DNow. Using a separate generator introduces some code
duplication, but is a simpler approach because of test-avx's extra
complexity to support 3- and 4-operand AVX instructions.
If needed, a common library can be introduced later.
While at it, for consistency move all the -cpu max rules to the
same place.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
show more ...
|
| #
61fd710b |
| 02-Sep-2022 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* SCSI fixes for Mac OS 9
* Fix CPU reset for x86/KVM nested virtualization state
* remove feature_not_found() from the confi
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* SCSI fixes for Mac OS 9
* Fix CPU reset for x86/KVM nested virtualization state
* remove feature_not_found() from the configure script
* Meson cleanups from muon
* improved i386 TCG tests for BMI and SSE
* SSE bugfixes
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# gpg: Signature made Thu 01 Sep 2022 14:23:00 EDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (39 commits)
target/i386: AVX+AES helpers prep
target/i386: AVX pclmulqdq prep
target/i386: Rewrite blendv helpers
target/i386: Misc AVX helper prep
target/i386: Destructive FP helpers for AVX
target/i386: Dot product AVX helper prep
target/i386: reimplement AVX comparison helpers
target/i386: Floating point arithmetic helper AVX prep
target/i386: Destructive vector helpers for AVX
target/i386: Misc integer AVX helper prep
target/i386: Rewrite simple integer vector helpers
target/i386: Rewrite vector shift helper
target/i386: rewrite destructive 3DNow operations
target/i386: Add CHECK_NO_VEX
target/i386: do not cast gen_helper_* function pointers
target/i386: Add size suffix to vector FP helpers
target/i386: isolate MMX code more
target/i386: check SSE table flags instead of hardcoding opcodes
target/i386: Move 3DNOW decoder
target/i386: Rework sse_op_table6/7
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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| #
91117bc5 |
| 24-Apr-2022 |
Paul Brook <paul@nowt.org> |
tests/tcg: i386: add SSE tests
Tests for correct operation of most x86-64 SSE instructions.
It should cover all combinations of overlapping register and memory
operands on a set of random-ish data.
tests/tcg: i386: add SSE tests
Tests for correct operation of most x86-64 SSE instructions.
It should cover all combinations of overlapping register and memory
operands on a set of random-ish data.
Results are bit-identical to an Intel i5-8500, with the exception of
the RCPSS and RSQRT approximations where the real CPU gives less accurate
results (the Intel spec allows relative errors up to 1.5 * 2^-12)
Signed-off-by: Paul Brook <paul@nowt.org>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220424220204.2493824-42-paul@nowt.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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