Revision tags: v9.2.0, v9.1.2, v9.1.1 |
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#
a53b9316 |
| 25-Sep-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
trivial patches for 2024-09-20
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEZKoqtTHVaQM2a/75gqpKJDselHgFAmbtJJU
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
trivial patches for 2024-09-20
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* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (22 commits) license: Update deprecated SPDX tag GPL-2.0 to GPL-2.0-only license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later license: Update deprecated SPDX tag LGPL-2.0+ to LGPL-2.0-or-later license: Simplify GPL-2.0-or-later license descriptions tests/functional: Correct typo in test_netdev_ethtool.py SPDX tag tests/bench: Rename test_akcipher_keys.inc -> test_akcipher_keys.c.inc target/hexagon: Rename macros.inc -> macros.h.inc tests/functional: Put the or1k_sim test into the slow category tests/qemu-iotests/testenv: Use the "r2d" machine for sh4/sh4eb tests/qemu-iotests/testenv: Use the "virt" machine for or1k util/cutils: Remove unused qemu_get_exec_dir hw/sysbus: Remove unused sysbus_mmio_unmap envlist: Remove unused envlist_parse hw/display: Fix mirrored output in dm163 hw/virtio/Kconfig: Include vhost-user-scmi only on arm targets tests/unit: Really build pbkdf test on macOS hw/loongarch/virt: Add description for virt machine type hw/mips/jazz: fix typo in in-built NIC alias ppc: fix incorrect spelling of PowerMac linux-user/syscall.c: eliminate other explicit LFS usages ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
97d348cc |
| 11-Sep-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later
The 'GPL-2.0+' license identifier has been deprecated since license list version 2.0rc2 [1] and replaced by the 'GPL-2.0-or-later' [2
license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later
The 'GPL-2.0+' license identifier has been deprecated since license list version 2.0rc2 [1] and replaced by the 'GPL-2.0-or-later' [2] tag.
[1] https://spdx.org/licenses/GPL-2.0+.html [2] https://spdx.org/licenses/GPL-2.0-or-later.html
Mechanical patch running:
$ sed -i -e s/GPL-2.0+/GPL-2.0-or-later/ \ $(git grep -lP 'SPDX-License-Identifier: \W+GPL-2.0\+[ $]' \ | egrep -v '^linux-headers|^include/standard-headers')
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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Revision tags: v9.1.0 |
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#
fd87be1d |
| 26-Apr-2024 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging
Accelerators patches
A lot of trivial cleanups and simplifications (moving methods around, adding/removing #include stateme
Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging
Accelerators patches
A lot of trivial cleanups and simplifications (moving methods around, adding/removing #include statements). Most notable changes:
- Rename NEED_CPU_H -> COMPILING_PER_TARGET - Rename few template headers using the '.h.inc' suffix - Extract some definitions / declarations into their own header: - accel/tcg/user-retaddr.h (helper_retaddr) - include/exec/abi_ptr.h (abi_ptr) - include/exec/breakpoint.h (CPUBreakpoint, CPUWatchpoint) - include/exec/mmu-access-type.h (MMUAccessType) - include/user/tswap-target.h (tswapl, bswaptls)
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmYsAuEACgkQ4+MsLN6t # wN78Rg//V9UoE0U9Lh6Sd2WpcSAYP9D1CBa+iGXhrmel0utER1sQLu022nvcLdHc # XtCgtX3H0yECF8dPX02rVp8IbSlOv3c8N/a6BxD79cRGqgXBYR/dEUqfXqeLJn3l # a58YU3i7sLNQ0l7VnwTiBnI0lw170/xJl2B2mcR1SvWuH3dr5vTeIXNureu36ORo # rc0oqWHbw1Pyyn8ADE2kPyFCOiwPwvcOvAk8dXGfib+mNCwNVV+ZUtAPi711VD8d # 9VW2gu2sXwnWdpROrSugSw+aPVF4UjltL9qJEl5bxoqWFmlET1Zn2NpKvsocUXmh # CMQQS2Tr4LpaaVQJGxx0yUe0B65X5+gCkIhsMOubED7GRyTCjrkOPm6exz3ge6WV # YmIboggFAk3OjAzLs7yZVkWsTK1Y3+3eX0u7AWPUsUu7rCT/Toc6QxDS7eT2hJfq # UDXI355PGbImgiArQa+OsT7v1Le4/iQa+TfN4fdUDpxEdfaxhnijWh+E91CEp+w/ # Mq7db9Z1aMnhFKIKdkPYyfwB74yXQrmYchJ0QojZjbzqNGwkt9VeC7O9RcYjEaHM # hMIexwccxexqGH22wn8vPd6ZVKtiLaG4AXO0v6Dn2YJ7/zb/ntcI6lRZqdBAHKNK # MzkjTRRRR0wAfu8Lk8CaNNEqUP4Po43fbYymo6AZhIR8NqfApL0= # =ifBx # -----END PGP SIGNATURE----- # gpg: Signature made Fri 26 Apr 2024 12:39:13 PM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
* tag 'accel-20240426' of https://github.com/philmd/qemu: (38 commits) plugins: Include missing 'qemu/bitmap.h' header hw/core: Avoid including the full 'hw/core/cpu.h' in 'tcg-cpu-ops.h' exec: Move CPUTLBEntry helpers to cputlb.c exec: Restrict inclusion of 'user/guest-base.h' exec: Rename 'exec/user/guest-base.h' as 'user/guest-base.h' exec: Restrict 'cpu_ldst.h' to TCG accelerator exec: Restrict TCG specific declarations of 'cputlb.h' exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header exec: Declare MMUAccessType type in 'mmu-access-type.h' header exec: Declare abi_ptr type in its own 'abi_ptr.h' header exec/user: Do not include 'cpu.h' in 'abitypes.h' exec: Move [b]tswapl() declarations to 'exec/user/tswap-target.h' exec: Declare target_words_bigendian() in 'exec/tswap.h' exec/cpu-all: Remove unused tswapls() definitions exec/cpu-all: Remove unused 'qemu/thread.h' header exec/cpu-all: Reduce 'qemu/rcu.h' header inclusion accel/hvf: Use accel-specific per-vcpu @dirty field accel/nvmm: Use accel-specific per-vcpu @dirty field accel/whpx: Use accel-specific per-vcpu @dirty field accel/tcg: Rename helper-head.h -> helper-head.h.inc ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
e92dd332 |
| 05-Dec-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'
accel/tcg/ files requires the following definitions:
- TARGET_LONG_BITS - TARGET_PAGE_BITS - TARGET_PHYS_ADDR_SPACE_BITS - TCG_GUEST_DEF
target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'
accel/tcg/ files requires the following definitions:
- TARGET_LONG_BITS - TARGET_PAGE_BITS - TARGET_PHYS_ADDR_SPACE_BITS - TCG_GUEST_DEFAULT_MO
The first 3 are defined in "cpu-param.h". The last one in "cpu.h", with a bunch of definitions irrelevant for TCG. By moving the TCG_GUEST_DEFAULT_MO definition to "cpu-param.h", we can simplify various accel/tcg includes.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20231211212003.21686-4-philmd@linaro.org>
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Revision tags: v8.0.0 |
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#
27a03171 |
| 14-Mar-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into staging
accel/tcg: Fix NB_MMU_MODES to 16 Balance of the target/ patchset which eliminates tcg_temp_free Balance of the target/
Merge tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu into staging
accel/tcg: Fix NB_MMU_MODES to 16 Balance of the target/ patchset which eliminates tcg_temp_free Balance of the target/ patchset which eliminates tcg_const
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmQPcb0dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV885AgAjDbg1soRBy0THf0X # CVXmQ4yYyUKAonZBL8Abt9yX01BhLFqEsrju3HiaLNOM9DbwWQ4gdvSrtAZ/K2YG # d6EvC+rJe79pr58MEEhqO4OO1ymp52amRHtEXva4vcKRNuM9WF5by/Hz2PsZyenG # ysaLBdddooA9SJeL7xYBMpKWFgUm3C8NzfaRfCBVcG94er9u8RUi0kx+drmOLw0g # vZ3Hekvi2I8Y5mWqvHeAIOsr8Md9PO3ezWxEteE4qsPNTTRfVD93oSGe9nNCYZTX # wWU51Vfv9GB6hOylAfMRIeCmkjks/gqLOGElsh1MaVovNDTXS5IKV/HgaLaocJHV # 2P81uQ== # =FpIY # -----END PGP SIGNATURE----- # gpg: Signature made Mon 13 Mar 2023 18:55:57 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20230313' of https://gitlab.com/rth7680/qemu: (91 commits) tcg: Drop tcg_const_* tcg: Drop tcg_const_*_vec target/tricore: Use min/max for saturate target/ppc: Avoid tcg_const_* in translate.c target/ppc: Fix gen_tlbsx_booke206 target/ppc: Rewrite trans_ADDG6S target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc target/ppc: Avoid tcg_const_* in fp-impl.c.inc target/ppc: Avoid tcg_const_* in vsx-impl.c.inc target/ppc: Avoid tcg_const_* in xxeval target/ppc: Avoid tcg_const_* in vmx-impl.c.inc target/ppc: Avoid tcg_const_i64 in do_vcntmb target/m68k: Use tcg_constant_i32 in gen_ea_mode target/arm: Avoid tcg_const_ptr in handle_rev target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn target/arm: Avoid tcg_const_* in translate-mve.c target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} target/arm: Improve trans_BFCI target/arm: Create gen_set_rmode, gen_restore_rmode ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
4c5b26e0 |
| 06-Mar-2023 |
Anton Johansson <anjo@rev.ng> |
target/s390x: Remove `NB_MMU_MODES` define
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Revi
target/s390x: Remove `NB_MMU_MODES` define
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230306175230.7110-19-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.2.0 |
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#
ec11dc41 |
| 11-May-2022 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-misc-2022-05-11' of git://repo.or.cz/qemu/armbru into staging
Miscellaneous patches patches for 2022-05-11
# -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AO
Merge tag 'pull-misc-2022-05-11' of git://repo.or.cz/qemu/armbru into staging
Miscellaneous patches patches for 2022-05-11
# -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmJ7zwISHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZThuAQAJdSuj5fpY8EXxhuS3Rc8uHPrz6lP+nZ # kwxKPOldwFdmkXRJ8qrjcc/BXxiJU3pxmSRvFZ8miCFMrb4Vd16sUzD6PeKb1jr8 # JsrvXcsaWn4f/p0v0WraamwSQeZUMjqsZPgZut93qfJoKmgTaxoZnR+ZDHFKoQJS # qBrHL/5+RPxSugLa6IEpSQwy80jd0tMBaG/e8V+JxzgFM5jzOExwXtfUujzS92Lr # NgapnbEZrpqErBC1xhpetQ8Q5I4r0kkLj4Exm/ClNtIM2GByJxI8x2DE+NJZNDnm # g/tvVKUhEl6cOywQRajAJ/LrhUpVSkz6wsczv35rhRS+1FoCb+PRKr42SxZGI2rB # tZLYt4ouoSGk2pYiudoIBKsIR1Svu7Cmg4YzOL9yvqF0BS3cRDvPgm3QFvoeErjL # EML7b41zLdIkbvujsJ7HJqVL44QmMSu13PcLUtDvLh+ivpL9wIUQn3ji+rfsgqh+ # RYw4niJ9JO3N3/VwEhlymc9kRSTgZ6rdIWPrtQ5ACwTADAv30++opxAlksE6mo0m # TYrqyTG2FHGOKm+5Q4Lyx1heHJDUAE3dlRIhGt8KqD6UKlpSfIVIUU2ztjZK4JQ5 # n85LOLZkE9ejbvbpnLX8hgKfouVKKYwFagc/ZA649cIXvC8YDxdOwvhjEVCxa+V5 # dQbpQsekXf9G # =jOTx # -----END PGP SIGNATURE----- # gpg: Signature made Wed 11 May 2022 07:58:10 AM PDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [undefined] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* tag 'pull-misc-2022-05-11' of git://repo.or.cz/qemu/armbru: Clean up decorations and whitespace around header guards Normalize header guard symbol definition Clean up ill-advised or unusual header guards Clean up header guards that don't match their file name
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
4f31b54b |
| 06-May-2022 |
Markus Armbruster <armbru@redhat.com> |
Normalize header guard symbol definition
We commonly define the header guard symbol without an explicit value. Normalize the exceptions.
Done with scripts/clean-header-guards.pl.
Signed-off-by: Ma
Normalize header guard symbol definition
We commonly define the header guard symbol without an explicit value. Normalize the exceptions.
Done with scripts/clean-header-guards.pl.
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20220506134911.2856099-4-armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.0.0, v6.2.0, v6.1.0, v5.2.0, v5.0.0, v4.2.0 |
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#
a578cdfb |
| 10-Jun-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190610' into staging
Move softmmu tlb into CPUNegativeOffsetState
# gpg: Signature made Mon 10 Jun 2019 15:07:55 BST # gpg:
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190610' into staging
Move softmmu tlb into CPUNegativeOffsetState
# gpg: Signature made Mon 10 Jun 2019 15:07:55 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20190610: (39 commits) tcg/arm: Remove mostly unreachable tlb special case tcg/arm: Use LDRD to load tlb mask+table tcg/aarch64: Use LDP to load tlb mask+table cpu: Remove CPU_COMMON cpu: Move the softmmu tlb to CPUNegativeOffsetState cpu: Move icount_decr to CPUNegativeOffsetState cpu: Introduce CPUNegativeOffsetState cpu: Introduce cpu_set_cpustate_pointers cpu: Move ENV_OFFSET to exec/gen-icount.h target/xtensa: Use env_cpu, env_archcpu target/unicore32: Use env_cpu, env_archcpu target/tricore: Use env_cpu target/tilegx: Use env_cpu target/sparc: Use env_cpu, env_archcpu target/sh4: Use env_cpu, env_archcpu target/s390x: Use env_cpu, env_archcpu target/riscv: Use env_cpu, env_archcpu target/ppc: Use env_cpu, env_archcpu target/openrisc: Use env_cpu, env_archcpu target/nios2: Use env_cpu, env_archcpu ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v4.0.0, v4.0.0-rc1 |
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#
74433bf0 |
| 22-Mar-2019 |
Richard Henderson <richard.henderson@linaro.org> |
tcg: Split out target/arch/cpu-param.h
For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES.
Inclu
tcg: Split out target/arch/cpu-param.h
For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES.
Include this new file from exec/cpu-defs.h.
This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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