Merge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu into staging

First RISC-V PR for 8.1

* CPURISCVState related cleanup and simplification
* Refactor Zicond and reuse

Merge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu into staging

First RISC-V PR for 8.1

* CPURISCVState related cleanup and simplification
* Refactor Zicond and reuse in XVentanaCondOps
* Fix invalid riscv,event-to-mhpmcounters entry
* Support subsets of code size reduction extension
* Fix itrigger when icount is used
* Simplification for RVH related check and code style fix
* Add signature dump function for spike to run ACT tests
* Rework MISA writing
* Fix mstatus.MPP related support
* Use check for relationship between Zdinx/Zhinx{min} and Zfinx
* Fix the H extension TVM trap
* A large collection of mstatus sum changes and cleanups
* Zero init APLIC internal state
* Implement query-cpu-definitions
* Restore the predicate() NULL check behavior
* Fix Guest Physical Address Translation
* Make sure an exception is raised if a pte is malformed
* Add Ventana's Veyron V1 CPU

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmRUU48ACgkQr3yVEwxT
# gBP6gxAAyhmz7dKOPIb8RtUR4IT+SQhKYZEoSewy4xlXazZvh03K0jiYlEKcPLG+
# al50WlwL8ISsYwwpnatQr0deoeXnz9+qrSv7ikrzyqZScS8JTcJb/pdQnOz6WK3s
# 3FCBnBsYyjpdV6a2uCC9qck7xKTUpa9Gjx06DOuIoLfS8aFvf7Z3EbvsEyyDTEIi
# kwB0j5kdQkJLyx993F3atupjZSxvFmLJdtU4+IVYiOeBEVRD1iZth9KB9L9zjA49
# s+qTHg+afEr3GDlR02So9hYxyHqTHgRI8gkPaVN+ReEErC0nJNcx7/7tEhsLsswY
# fUAmsMnXaYOnEWFTJ+D/161rKx6QXwkX7bYCmPJFLGmzw5LWdK7JHEoXylRffuay
# Zh2e2tNky7QXPqp9fU0DBb9Xpbr0wHorLqFT8X8cuaI6r92weunZHx9zulhm11WA
# m0Q1UZaqAsnIL98UZocZr6C1hzR/OJ2QfjHDsKuPJEi8ylb7yRi4adcPn8YGBYX+
# 4YDNSvanegQq0g7gO3kSV/Cqweqm2xoDQyiRdyHWLQK2yJiZJTy07unzi+H7Dubf
# JR9bkdHTKz6Ywrf8hqw4yRqk5sPyamxHdXbhTDohUaPPQcfwQUraRdxIv1AQ94A1
# j+msUYpIZHjb5q2DtNHI1hQMdkVGRLMlfA8kpB+EcY1sXiqSky8=
# =fVG8
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 05 May 2023 01:53:35 AM BST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu: (89 commits)
target/riscv: add Ventana's Veyron V1 CPU
riscv: Make sure an exception is raised if a pte is malformed
target/riscv: Fix Guest Physical Address Translation
target/riscv: Restore the predicate() NULL check behavior
target/riscv: add TYPE_RISCV_DYNAMIC_CPU
target/riscv: add query-cpy-definitions support
target/riscv: add CPU QOM header
hw/intc/riscv_aplic: Zero init APLIC internal state
target/riscv: Reorg sum check in get_physical_address
target/riscv: Reorg access check in get_physical_address
target/riscv: Merge checks for reserved pte flags
target/riscv: Don't modify SUM with is_debug
target/riscv: Suppress pte update with is_debug
target/riscv: Move leaf pte processing out of level loop
target/riscv: Hoist pbmte and hade out of the level loop
target/riscv: Hoist second stage mode change to callers
target/riscv: Check SUM in the correct register
target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
target/riscv: Move hstatus.spvp check to check_access_hlsv
target/riscv: Introduce mmuidx_2stage
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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target/riscv: Simplify type conversion for CPURISCVState

Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp, since type converts from CPURISCVState to
RISCV

target/riscv: Simplify type conversion for CPURISCVState

Use CPURISCVState as argument directly in riscv_cpu_update_mip and
riscv_timer_write_timecmp, since type converts from CPURISCVState to
RISCVCPU in many caller of them and then back to CPURISCVState in them.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

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Merge tag 'pull-riscv-to-apply-20220907' of https://github.com/alistair23/qemu into staging

First RISC-V PR for QEMU 7.2

* Update [m|h]tinst CSR in interrupt handling
* Force disable extensions if

Merge tag 'pull-riscv-to-apply-20220907' of https://github.com/alistair23/qemu into staging

First RISC-V PR for QEMU 7.2

* Update [m|h]tinst CSR in interrupt handling
* Force disable extensions if priv spec version does not match
* fix shifts shamt value for rv128c
* move zmmul out of the experimental
* virt: pass random seed to fdt
* Add checks for supported extension combinations
* Upgrade OpenSBI to v1.1
* Fix typo and restore Pointer Masking functionality for RISC-V
* Add mask agnostic behaviour (rvv_ma_all_1s) for vector extension
* Add Zihintpause support
* opentitan: bump opentitan version
* microchip_pfsoc: fix kernel panics due to missing peripherals
* Remove additional priv version check for mcountinhibit
* virt machine device tree improvements
* Add xicondops in ISA entry
* Use official extension names for AIA CSRs

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmMYUCUACgkQIeENKd+X
# cFRpEQf/T1FFcGq3TZrEPmqMdFPUSb+SEJNgwYFfloqkNjB2HIFbd2tKWAE1Tgjr
# esV00p7YPyox1Ct+fKdwSxDxRSN9OI56v+nI8ZFwluVu7vpChuTFmOHur8rNxl1T
# 8MZgP2kMxMOJSnyHCS2iV9AUFdTExS65DbmlAKzi5fpBtt9jYTPSXsI49MP8+Ku/
# 1gdv5ZF5BXDJsGs7xHvE92dRzQEVN+As64IjlknFHHpmCM1b+Ah3GekXUbKmBuDG
# /NaZyZNPCYxdRmPm/D7k0SOMZSJ9sLyhXTetZ0ZpBxG1ioClX37yS5wn4NLsCz/2
# fXrnML+MQFUKZ03AZ9lWvxcu7kXfWA==
# =7mGD
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 07 Sep 2022 04:02:45 EDT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220907' of https://github.com/alistair23/qemu: (44 commits)
target/riscv: Update the privilege field for sscofpmf CSRs
hw/riscv: virt: Add PMU DT node to the device tree
target/riscv: Add few cache related PMU events
target/riscv: Simplify counter predicate function
target/riscv: Add sscofpmf extension support
target/riscv: Add vstimecmp support
target/riscv: Add stimecmp support
hw/intc: Move mtimer/mtimecmp to aclint
target/riscv: Use official extension names for AIA CSRs
target/riscv: Add xicondops in ISA entry
hw/core: fix platform bus node name
hw/riscv: virt: fix syscon subnode paths
hw/riscv: virt: fix the plic's address cells
hw/riscv: virt: fix uart node name
target/riscv: Remove additional priv version check for mcountinhibit
hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals
hw/riscv: opentitan: bump opentitan version
target/riscv: Fix priority of csr related check in riscv_csrrw_check
hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()
target/riscv: Add Zihintpause support
...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

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target/riscv: Add stimecmp support

stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified

target/riscv: Add stimecmp support

stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220824221357.41070-3-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...