Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20190904' into staging

Updates for arch v1.3.

# gpg: Signature made Wed 04 Sep 2019 21:30:41 BST
# gpg: using RSA key 7A481E7

Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20190904' into staging

Updates for arch v1.3.

# gpg: Signature made Wed 04 Sep 2019 21:30:41 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-or1k-20190904:
target/openrisc: Update cpu "any" to v1.3
target/openrisc: Implement l.adrp
target/openrisc: Implement move to/from FPCSR
target/openrisc: Implement unordered fp comparisons
target/openrisc: Add support for ORFPX64A32
target/openrisc: Check CPUCFG_OF32S for float insns
target/openrisc: Fix lf.ftoi.s
target/openrisc: Add VR2 and AVR special processor registers
target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init
target/openrisc: Make VR and PPC read-only
target/openrisc: Cache R0 in DisasContext
target/openrisc: Replace cpu register array with a function
target/openrisc: Add DisasContext parameter to check_r0_write

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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target/openrisc: Implement l.adrp

This was added to the 1.3 spec.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Implement unordered fp comparisons

These were added to the 1.3 spec. For OF32S, validate AVR.
But OF64A32 is itself new to 1.3 so no extra check needed.

Reviewed-by: Stafford Horn

target/openrisc: Implement unordered fp comparisons

These were added to the 1.3 spec. For OF32S, validate AVR.
But OF64A32 is itself new to 1.3 so no extra check needed.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/openrisc: Add support for ORFPX64A32

This is hardware support for double-precision floating-point using
pairs of 32-bit registers. Fix latent bugs in the heretofore unused
helper_itofd and h

target/openrisc: Add support for ORFPX64A32

This is hardware support for double-precision floating-point using
pairs of 32-bit registers. Fix latent bugs in the heretofore unused
helper_itofd and helper_ftoid. Include the bit for cpu "any".
Change the default cpu for linux-user to "any".

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-05-09' into staging

- Fix "make check" problem that occurred with LANG=C and Python 3.5 / 3.6
- Get rid of some more dependen

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-05-09' into staging

- Fix "make check" problem that occurred with LANG=C and Python 3.5 / 3.6
- Get rid of some more dependencies on the global_qtest variable in the qtests
- Some other small test clean-ups
- Some copyright statement clarifications
- Mark TARGET_FMT_lu as poisoned

# gpg: Signature made Thu 09 May 2019 08:45:47 BST
# gpg: using RSA key 2ED9D774FE702DB5
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5

* remotes/huth-gitlab/tags/pull-request-2019-05-09:
include/exec/poison: Mark TARGET_FMT_lu as poisoned, too
target/sh4: Fix LGPL information in the file headers
target/openrisc: Fix LGPL information in the file headers
hw/i2c/smbus_ich9: Fix the confusing contributions-after-2012 statement
tests: qpci_unplug_acpi_device_test() should not rely on global_qtest
tests/drive_del-test: Use qtest_init() instead of qtest_start()
tests/Makefile: Remove unused test-obj-y variable
tests/tpm-tests: Use g_test_skip() to mark skipped tests
tests/ide-test: Make test independent of global_qtest
tests/test-hmp: Use qtest_init() instead of qtest_start()
tests/qmp-cmd-test: Use qtest_init() instead of qtest_start()
tests/megasas: Make test independent of global_qtest
tests/tco: Make test independent of global_qtest
tests: Force Python I/O encoding for check-qapi-schema

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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target/openrisc: Fix LGPL information in the file headers

It's either "GNU *Library* General Public License version 2" or "GNU
Lesser General Public License version *2.1*", but there was no "version

target/openrisc: Fix LGPL information in the file headers

It's either "GNU *Library* General Public License version 2" or "GNU
Lesser General Public License version *2.1*", but there was no "version
2.0" of the "Lesser" license. So assume that version 2.1 is meant here.

Acked-by: Stafford Horne <shorne@gmail.com>
Message-Id: <1550073577-4248-1-git-send-email-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

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Merge remote-tracking branch 'remotes/rth/tags/tgt-openrisc-pull-request' into staging

Convert openrisc to decodetree.py

# gpg: Signature made Mon 14 May 2018 23:25:40 BST
# gpg: usi

Merge remote-tracking branch 'remotes/rth/tags/tgt-openrisc-pull-request' into staging

Convert openrisc to decodetree.py

# gpg: Signature made Mon 14 May 2018 23:25:40 BST
# gpg: using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/tgt-openrisc-pull-request:
target/openrisc: Merge disas_openrisc_insn
target/openrisc: Convert dec_float
target/openrisc: Convert dec_compi
target/openrisc: Convert dec_comp
target/openrisc: Convert dec_M
target/openrisc: Convert dec_logic
target/openrisc: Convert dec_mac
target/openrisc: Convert dec_calc
target/openrisc: Convert remainder of dec_misc insns
target/openrisc: Convert memory insns
target/openrisc: Convert branch insns
target/openrisc: Start conversion to decodetree.py
target-openrisc: Write back result before FPE exception

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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target/openrisc: Convert dec_float

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Convert dec_compi

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Convert dec_comp

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Convert dec_M

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Convert dec_logic

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Convert dec_mac

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Convert dec_calc

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Convert remainder of dec_misc insns

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Convert memory insns

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Convert branch insns

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Start conversion to decodetree.py

Begin with the 0x08 major opcode, the system instructions.

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.h

target/openrisc: Start conversion to decodetree.py

Begin with the 0x08 major opcode, the system instructions.

Acked-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...