Merge tag 'or1k-pull-request-20230513' of https://github.com/stffrdhrn/qemu into staging

OpenRISC FPU Updates for 8.1

A few fixes and updates to bring OpenRISC inline with the latest
architecture s

Merge tag 'or1k-pull-request-20230513' of https://github.com/stffrdhrn/qemu into staging

OpenRISC FPU Updates for 8.1

A few fixes and updates to bring OpenRISC inline with the latest
architecture spec updates:

- Allow FPCSR to be accessed in user mode
- Select tininess detection before rounding
- Fix FPE Exception PC value

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmRfPIEACgkQw7McLV5m
# J+RFuhAAt4xxci52fxvPpgUu/mjKU6mbYNjBEPEh+OAcb+m/BrvKhazZDACkyLMe
# ehavWtI856jfy6DsIA5wj5+zhgV8W5DR6a1mHIhmSAoVq7e+NnC5y0GJC9B0Xd/2
# FNOq/LZPtv/w7u+D1pFJaTb07hAaFVIC05Arn4dXa1k3yBuyjqIJnlrXa3Jt0pLW
# To/z1zch1rUp6RhFmGxU+8/qvTbzqkm/F3kbe8l2z34371lTd6KhPwvKaImMpTYQ
# dvULTMXjZ6Dp8BmUrDcnLMTL3NbYcPrI+qOHX1X+dwzNFyui2I8Ci7IfEKJ460ja
# Fe2Ku/aDfHSZYYayWaYSlrrZ1AH0fLLwIkHSs95+xUMsl81mtS6lIysj7fAFRnM5
# 7tU4ov1T/leupvvUCUX5N4Yje/yvbuoAqGyhjDHzJ98vIe6fDhutU4Bm8/30q6Dy
# nKnfSgRHrrTrH042xW32DJnzaN2pEWrNtOMaegLMaqZ60app2YDaKJvtHLua1VjD
# b+g+X/+xBNb34k5e/f4z+GeGPoqE2wvwMcSkD+NBE8je3idPdMS/u5lQrvqvcbI/
# DJBRoPifNME/oYoTxPVKRnrCQIWQ6YkeLWVmqMfCVpjCF97gexo+UBUawJimTXFr
# gmcIYxv87oKF4KbCn7LsLlXGSpWSihKSBTHDxFPaKiRbnYZ5ais=
# =zqbX
# -----END PGP SIGNATURE-----
# gpg: Signature made Sat 13 May 2023 08:30:09 AM BST
# gpg: using RSA key D9C47354AEF86C103A25EFF1C3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <shorne@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4

* tag 'or1k-pull-request-20230513' of https://github.com/stffrdhrn/qemu:
target/openrisc: Setup FPU for detecting tininess before rounding
target/openrisc: Set PC to cpu state on FPU exception
target/openrisc: Allow fpcsr access in user mode

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/openrisc: Set PC to cpu state on FPU exception

Store the PC to ensure the correct value can be read in the exception
handler.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Ri

target/openrisc: Set PC to cpu state on FPU exception

Store the PC to ensure the correct value can be read in the exception
handler.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth/tags/pull-fpu-20200519' into staging

Misc cleanups

# gpg: Signature made Tue 19 May 2020 16:51:38 BST
# gpg: using RSA key 7A481E78868B4DB6A

Merge remote-tracking branch 'remotes/rth/tags/pull-fpu-20200519' into staging

Misc cleanups

# gpg: Signature made Tue 19 May 2020 16:51:38 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-fpu-20200519:
softfloat: Return bool from all classification predicates
softfloat: Inline floatx80 compare specializations
softfloat: Inline float128 compare specializations
softfloat: Inline float64 compare specializations
softfloat: Inline float32 compare specializations
softfloat: Name compare relation enum
softfloat: Name rounding mode enum
softfloat: Change tininess_before_rounding to bool
softfloat: Replace flag with bool
softfloat: Use post test for floatN_mul

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

softfloat: Name compare relation enum

Give the previously unnamed enum a typedef name. Use it in the
prototypes of compare functions. Use it to hold the results
of the compare functions.

Reviewed

softfloat: Name compare relation enum

Give the previously unnamed enum a typedef name. Use it in the
prototypes of compare functions. Use it to hold the results
of the compare functions.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20200116' into staging

Fix FPSCR masking

# gpg: Signature made Fri 17 Jan 2020 00:51:41 GMT
# gpg: using RSA key 7A481E78868B

Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20200116' into staging

Fix FPSCR masking

# gpg: Signature made Fri 17 Jan 2020 00:51:41 GMT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-or1k-20200116:
target/openrisc: Fix FPCSR mask to allow setting DZF

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/openrisc: Fix FPCSR mask to allow setting DZF

The mask used when setting FPCSR allows setting bits 10 to 1. However,
OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
Fl

target/openrisc: Fix FPCSR mask to allow setting DZF

The mask used when setting FPCSR allows setting bits 10 to 1. However,
OpenRISC has flags and config bits in 11 to 1, 11 being Divide by Zero
Flag (DZF). This seems like an off-by-one bug.

This was found when testing the GLIBC test suite which has test cases to
set and clear all bits.

Signed-off-by: Stafford Horne <shorne@gmail.com>
Message-Id: <20200110212843.27335-1-shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20190904' into staging

Updates for arch v1.3.

# gpg: Signature made Wed 04 Sep 2019 21:30:41 BST
# gpg: using RSA key 7A481E7

Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20190904' into staging

Updates for arch v1.3.

# gpg: Signature made Wed 04 Sep 2019 21:30:41 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-or1k-20190904:
target/openrisc: Update cpu "any" to v1.3
target/openrisc: Implement l.adrp
target/openrisc: Implement move to/from FPCSR
target/openrisc: Implement unordered fp comparisons
target/openrisc: Add support for ORFPX64A32
target/openrisc: Check CPUCFG_OF32S for float insns
target/openrisc: Fix lf.ftoi.s
target/openrisc: Add VR2 and AVR special processor registers
target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init
target/openrisc: Make VR and PPC read-only
target/openrisc: Cache R0 in DisasContext
target/openrisc: Replace cpu register array with a function
target/openrisc: Add DisasContext parameter to check_r0_write

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/openrisc: Implement move to/from FPCSR

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc: Implement unordered fp comparisons

These were added to the 1.3 spec. For OF32S, validate AVR.
But OF64A32 is itself new to 1.3 so no extra check needed.

Reviewed-by: Stafford Horn

target/openrisc: Implement unordered fp comparisons

These were added to the 1.3 spec. For OF32S, validate AVR.
But OF64A32 is itself new to 1.3 so no extra check needed.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/openrisc: Add support for ORFPX64A32

This is hardware support for double-precision floating-point using
pairs of 32-bit registers. Fix latent bugs in the heretofore unused
helper_itofd and h

target/openrisc: Add support for ORFPX64A32

This is hardware support for double-precision floating-point using
pairs of 32-bit registers. Fix latent bugs in the heretofore unused
helper_itofd and helper_ftoid. Include the bit for cpu "any".
Change the default cpu for linux-user to "any".

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/openrisc: Fix lf.ftoi.s

The specification of this insn is round-to-zero.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-05-09' into staging

- Fix "make check" problem that occurred with LANG=C and Python 3.5 / 3.6
- Get rid of some more dependen

Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-05-09' into staging

- Fix "make check" problem that occurred with LANG=C and Python 3.5 / 3.6
- Get rid of some more dependencies on the global_qtest variable in the qtests
- Some other small test clean-ups
- Some copyright statement clarifications
- Mark TARGET_FMT_lu as poisoned

# gpg: Signature made Thu 09 May 2019 08:45:47 BST
# gpg: using RSA key 2ED9D774FE702DB5
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5

* remotes/huth-gitlab/tags/pull-request-2019-05-09:
include/exec/poison: Mark TARGET_FMT_lu as poisoned, too
target/sh4: Fix LGPL information in the file headers
target/openrisc: Fix LGPL information in the file headers
hw/i2c/smbus_ich9: Fix the confusing contributions-after-2012 statement
tests: qpci_unplug_acpi_device_test() should not rely on global_qtest
tests/drive_del-test: Use qtest_init() instead of qtest_start()
tests/Makefile: Remove unused test-obj-y variable
tests/tpm-tests: Use g_test_skip() to mark skipped tests
tests/ide-test: Make test independent of global_qtest
tests/test-hmp: Use qtest_init() instead of qtest_start()
tests/qmp-cmd-test: Use qtest_init() instead of qtest_start()
tests/megasas: Make test independent of global_qtest
tests/tco: Make test independent of global_qtest
tests: Force Python I/O encoding for check-qapi-schema

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/openrisc: Fix LGPL information in the file headers

It's either "GNU *Library* General Public License version 2" or "GNU
Lesser General Public License version *2.1*", but there was no "version

target/openrisc: Fix LGPL information in the file headers

It's either "GNU *Library* General Public License version 2" or "GNU
Lesser General Public License version *2.1*", but there was no "version
2.0" of the "Lesser" license. So assume that version 2.1 is meant here.

Acked-by: Stafford Horne <shorne@gmail.com>
Message-Id: <1550073577-4248-1-git-send-email-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

Merge remote-tracking branch 'remotes/rth/tags/tgt-openrisc-pull-request' into staging

Convert openrisc to decodetree.py

# gpg: Signature made Mon 14 May 2018 23:25:40 BST
# gpg: usi

Merge remote-tracking branch 'remotes/rth/tags/tgt-openrisc-pull-request' into staging

Convert openrisc to decodetree.py

# gpg: Signature made Mon 14 May 2018 23:25:40 BST
# gpg: using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/tgt-openrisc-pull-request:
target/openrisc: Merge disas_openrisc_insn
target/openrisc: Convert dec_float
target/openrisc: Convert dec_compi
target/openrisc: Convert dec_comp
target/openrisc: Convert dec_M
target/openrisc: Convert dec_logic
target/openrisc: Convert dec_mac
target/openrisc: Convert dec_calc
target/openrisc: Convert remainder of dec_misc insns
target/openrisc: Convert memory insns
target/openrisc: Convert branch insns
target/openrisc: Start conversion to decodetree.py
target-openrisc: Write back result before FPE exception

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target-openrisc: Write back result before FPE exception

The architecture manual is unclear about this, but the or1ksim
does writeback before the exception. This requires splitting
the helpers in ha

target-openrisc: Write back result before FPE exception

The architecture manual is unclear about this, but the or1ksim
does writeback before the exception. This requires splitting
the helpers in half, with the exception raised by the second.

Acked-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>

show more ...

Merge remote-tracking branch 'remotes/stsquad/tags/pull-softfloat-refactor-210218-1' into staging

This is the re-factor of softfloat:

- shared common code path float16/32/64
- well commented an

Merge remote-tracking branch 'remotes/stsquad/tags/pull-softfloat-refactor-210218-1' into staging

This is the re-factor of softfloat:

- shared common code path float16/32/64
- well commented and easy to follow code
- added a bunch of float16 support

While some operations are slower the key ones exercised by the
floating point dbt-bench are the same: https://i.imgur.com/oXNJNql.png

# gpg: Signature made Wed 21 Feb 2018 10:44:14 GMT
# gpg: using RSA key FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>"
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-softfloat-refactor-210218-1: (22 commits)
fpu/softfloat: re-factor sqrt
fpu/softfloat: re-factor compare
fpu/softfloat: re-factor minmax
fpu/softfloat: re-factor scalbn
fpu/softfloat: re-factor int/uint to float
fpu/softfloat: re-factor float to int/uint
fpu/softfloat: re-factor round_to_int
fpu/softfloat: re-factor muladd
fpu/softfloat: re-factor div
fpu/softfloat: re-factor mul
fpu/softfloat: re-factor add/sub
fpu/softfloat: define decompose structures
fpu/softfloat: move the extract functions to the top of the file
fpu/softfloat: improve comments on ARM NaN propagation
include/fpu/softfloat: add some float16 constants
include/fpu/softfloat: implement float16_set_sign helper
include/fpu/softfloat: implement float16_chs helper
include/fpu/softfloat: implement float16_abs helper
target/*/cpu.h: remove softfloat.h
fpu/softfloat-types: new header to prevent excessive re-builds
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/*/cpu.h: remove softfloat.h

As cpu.h is another typically widely included file which doesn't need
full access to the softfloat API we can remove the includes from here
as well. Where they do

target/*/cpu.h: remove softfloat.h

As cpu.h is another typically widely included file which doesn't need
full access to the softfloat API we can remove the includes from here
as well. Where they do need types it's typically for float_status and
the rounding modes so we move that to softfloat-types.h as well.

As a result of not having softfloat in every cpu.h call we now need to
add it to various helpers that do need the full softfloat.h
definitions.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[For PPC parts]
Acked-by: David Gibson <david@gibson.dropbear.id.au>

show more ...

Merge remote-tracking branch 'remotes/rth/tags/pull-or-20170214' into staging

Queued openrisc patches

# gpg: Signature made Mon 13 Feb 2017 21:21:03 GMT
# gpg: using RSA key 0xAD1270

Merge remote-tracking branch 'remotes/rth/tags/pull-or-20170214' into staging

Queued openrisc patches

# gpg: Signature made Mon 13 Feb 2017 21:21:03 GMT
# gpg: using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg: aka "Richard Henderson <rth@redhat.com>"
# gpg: aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-or-20170214: (24 commits)
target/openrisc: Optimize for r0 being zero
target/openrisc: Tidy handling of delayed branches
target/openrisc: Tidy ppc/npc implementation
target/openrisc: Optimize l.jal to next
target/openrisc: Fix madd
target/openrisc: Implement muld, muldu, macu, msbu
target/openrisc: Represent MACHI:MACLO as a single unit
target/openrisc: Implement msync
target/openrisc: Enable trap, csync, msync, psync for user mode
target/openrisc: Set flags on helpers
target/openrisc: Use movcond where appropriate
target/openrisc: Keep SR_CY and SR_OV in a separate variables
target/openrisc: Keep SR_F in a separate variable
target/openrisc: Invert the decoding in dec_calc
target/openrisc: Put SR[OVE] in TB flags
target/openrisc: Streamline arithmetic and OVE
target/openrisc: Rationalize immediate extraction
target/openrisc: Tidy insn dumping
target/openrisc: Implement lwa, swa
target/openrisc: Fix exception handling status registers
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/openrisc: Fix madd

Note that the specification for lf.madd.s is confused. It's
the only mention of supposed FPMADDHI/FPMADDLO special registers.
On the other hand, or1ksim implements a somew

target/openrisc: Fix madd

Note that the specification for lf.madd.s is confused. It's
the only mention of supposed FPMADDHI/FPMADDLO special registers.
On the other hand, or1ksim implements a somewhat normal non-fused
multiply and add. Mirror that.

Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>

show more ...

Merge remote-tracking branch 'remotes/huth/tags/target-dirs-20161220' into staging

Move target-xxx folders to target/ directory

# gpg: Signature made Tue 20 Dec 2016 21:00:39 GMT
# gpg:

Merge remote-tracking branch 'remotes/huth/tags/target-dirs-20161220' into staging

Move target-xxx folders to target/ directory

# gpg: Signature made Tue 20 Dec 2016 21:00:39 GMT
# gpg: using RSA key 0x2ED9D774FE702DB5
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>"
# gpg: aka "Thomas Huth <thuth@redhat.com>"
# gpg: aka "Thomas Huth <huth@tuxfamily.org>"
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5

* remotes/huth/tags/target-dirs-20161220:
Move target-* CPU file into a target/ folder

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Move target-* CPU file into a target/ folder

We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V,

Move target-* CPU file into a target/ folder

We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V, AVR) are likely to be included soon, too, so the main
folder of the QEMU sources slowly gets quite overcrowded with the
target-xxx folders.
To disburden the main folder a little bit, let's move the target-xxx
folders into a dedicated target/ folder, so that target-xxx/ simply
becomes target/xxx/ instead.

Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part]
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part]
Acked-by: Michael Walle <michael@walle.cc> [lm32 part]
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part]
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part]
Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part]
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part]
Acked-by: Richard Henderson <rth@twiddle.net> [alpha part]
Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part]
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part]
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part]
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part]
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...