Merge remote-tracking branch 'remotes/philmd/tags/mips-20210825' into staging

MIPS patches queue

- minor simplifications in PREF / JR opcodes
- merge 32-bit/64-bit Release6 decodetree definitions
-

Merge remote-tracking branch 'remotes/philmd/tags/mips-20210825' into staging

MIPS patches queue

- minor simplifications in PREF / JR opcodes
- merge 32-bit/64-bit Release6 decodetree definitions
- converted NEC Vr54xx extension opcodes to decodetree
- housekeeping in gen_helper() macros
- replace TARGET_WORDS_BIGENDIAN #ifdef'ry by cpu_is_bigendian()
- allow Loongson 3A1000 to use up to 48-bit VAddr

# gpg: Signature made Wed 25 Aug 2021 12:04:31 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210825: (28 commits)
target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()
target/mips: Store CP0_Config0 in DisasContext
target/mips: Replace GET_LMASK64() macro by get_lmask(64) function
target/mips: Replace GET_LMASK() macro by get_lmask(32) function
target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers
target/mips: Define gen_helper() macros in translate.h
target/mips: Use tcg_constant_i32() in generate_exception_err()
target/mips: Inline gen_helper_0e0i()
target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros
target/mips: Simplify gen_helper() macros by using tcg_constant_i32()
target/mips: Use tcg_constant_i32() in gen_helper_0e2i()
target/mips: Remove gen_helper_1e2i()
target/mips: Remove gen_helper_0e3i()
target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT
target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
target/mips: Document Loongson-3A CPU definitions
target/mips: Convert Vr54xx MSA* opcodes to decodetree
target/mips: Convert Vr54xx MUL* opcodes to decodetree
target/mips: Convert Vr54xx MACC* opcodes to decodetree
target/mips: Introduce decodetree structure for NEC Vr54xx extension
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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target/mips: Convert Vr54xx MSA* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

* MSAC Multiply, negate, accumulate, and move LO
* MSACHI Multiply,

target/mips: Convert Vr54xx MSA* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

* MSAC Multiply, negate, accumulate, and move LO
* MSACHI Multiply, negate, accumulate, and move HI
* MSACHIU Unsigned multiply, negate, accumulate, and move HI
* MSACU Unsigned multiply, negate, accumulate, and move LO

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-8-f4bug@amsat.org>

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target/mips: Convert Vr54xx MUL* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

* MULHI Multiply and move HI
* MULHIU Unsigned multiply and move HI

target/mips: Convert Vr54xx MUL* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

* MULHI Multiply and move HI
* MULHIU Unsigned multiply and move HI
* MULS Multiply, negate, and move LO
* MULSHI Multiply, negate, and move HI
* MULSHIU Unsigned multiply, negate, and move HI
* MULSU Unsigned multiply, negate, and move LO

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-7-f4bug@amsat.org>

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target/mips: Convert Vr54xx MACC* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

* MACC Multiply, accumulate, and move LO
* MACCHI Multiply, accumu

target/mips: Convert Vr54xx MACC* opcodes to decodetree

Convert the following Integer Multiply-Accumulate opcodes:

* MACC Multiply, accumulate, and move LO
* MACCHI Multiply, accumulate, and move HI
* MACCHIU Unsigned multiply, accumulate, and move HI
* MACCU Unsigned multiply, accumulate, and move LO

Since all opcodes are generated using the same pattern, we
add the gen_helper_mult_acc_t typedef and MULT_ACC() macro
to remove boilerplate code.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210808173018.90960-6-f4bug@amsat.org>

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target/mips: Introduce decodetree structure for NEC Vr54xx extension

The decoder is called but doesn't decode anything. This will
ease reviewing the next commit.

Signed-off-by: Philippe Mathieu-Dau

target/mips: Introduce decodetree structure for NEC Vr54xx extension

The decoder is called but doesn't decode anything. This will
ease reviewing the next commit.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801235926.3178085-3-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

show more ...