Merge tag 'pull-maintainer-9.1-rc0-230724-1' of https://gitlab.com/stsquad/qemu into staging

Maintainer updates for testing, gdbstub, semihosting, plugins

- bump python in *BSD images via libvirt

Merge tag 'pull-maintainer-9.1-rc0-230724-1' of https://gitlab.com/stsquad/qemu into staging

Maintainer updates for testing, gdbstub, semihosting, plugins

- bump python in *BSD images via libvirt-ci
- remove old unused Leon3 Avocado test
- re-factor gdb command extension
- add stoptrigger plugin to contrib
- ensure plugin mem callbacks properly sized
- reduce check-tcg noise of inline plugin test
- fix register dumping in execlog plugin
- restrict semihosting to TCG builds
- fix regex in MTE test

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmae5OcACgkQ+9DbCVqe
# KkR8cgf/eM2Sm7EG7zIQ8SbY53DS07ls6uT7Mfn4374GEmj4Cy1I+WNoLGM5vq1r
# qWAC9q2LgJVMQoWJA6Fi3SCKiylBp3/jIdJ7CWN5qj/NmePHSV3EisQXf2qOWWL9
# qOX2hJI7IIYNI2v3IvCzN/fB8F8U60iXERFHRypBH2p6Mz+EGMC3CEhesOEUta6o
# 2IMkRW8MoDv9x4B+FnNYav6CfqZjhRenu1CGgVGvWYRds2QDVNB/14kOunmBuwSs
# gPb7AhhnpobDYVxMarlJNPMbOdFjtDkYCajCNW7ffLcl+OjhoVR6cJcFpbOMv4kZ
# 8Nok8aDjUDWwUbmU0rBynca+1k8OTg==
# =TjRc
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 23 Jul 2024 09:01:59 AM AEST
# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]

* tag 'pull-maintainer-9.1-rc0-230724-1' of https://gitlab.com/stsquad/qemu:
tests/tcg/aarch64: Fix test-mte.py
semihosting: Restrict to TCG
target/xtensa: Restrict semihosting to TCG
target/riscv: Restrict semihosting to TCG
target/mips: Restrict semihosting to TCG
target/m68k: Restrict semihosting to TCG
target/mips: Add semihosting stub
target/m68k: Add semihosting stub
semihosting: Include missing 'gdbstub/syscalls.h' header
plugins/execlog.c: correct dump of registers values
tests/plugins: use qemu_plugin_outs for inline stats
plugins: fix mem callback array size
plugins/stoptrigger: TCG plugin to stop execution under conditions
gdbstub: Re-factor gdb command extensions
tests/avocado: Remove non-working sparc leon3 test
testing: bump to latest libvirt-ci

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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target/mips: Add semihosting stub

Since the SEMIHOSTING feature is optional, we need
a stub to link when it is disabled.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240

target/mips: Add semihosting stub

Since the SEMIHOSTING feature is optional, we need
a stub to link when it is disabled.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240717105723.58965-4-philmd@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240718094523.1198645-11-alex.bennee@linaro.org>

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Merge tag 'mips-20230710' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Use clock API & divider for cp0_timer to avoid rounding issue (Jiaxun)
- Implement Loongson CSR instruc

Merge tag 'mips-20230710' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Use clock API & divider for cp0_timer to avoid rounding issue (Jiaxun)
- Implement Loongson CSR instructions (Jiaxun)
- Implement Ingenic MXU ASE v1 rev2 (Siarhei)
- Enable GINVx support for I6400 and I6500 cores (Marcin)
- Generalize PCI IDE controller models (Bernhard)

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmSsg5kACgkQ4+MsLN6t
# wN6O4g/9GpirNnG1tizIEksI17PaAotgui2PYzml2nQLyQNmPs3lSfyDEfFpZLC6
# HGxglNjdvCgmIhRH1IuRKuJofp0r84NY+sktXjz2+As3opyjR66gVsSefWeupr7t
# avZQQIBBOV3OYLzFkqjDpBflyKXz43MRW3r9ai4Dle/TwiE5GA1iKuQ6Rt55urtT
# 045OdtFZTsIwTyg75pSXExAehOn5FQ4aqIODwfJYqvhkkVZ9lgWYSgUOsgDcGqPQ
# eytpif6+m350Xme4BgqITMZkeIbyKcCcfU37JBqk/q6/gDDf18zSWpC7MNXea4ZR
# so9ffZqms/xcIOfIO3uc4t9AZRHchiVjFHihCUKc0mBTzLy1QhQ4ybdQu3fUywaG
# WziEFLrJ/qfWjixRxeDdBZamC2fSxYtcRNST7g+XttiMacvQC6aPFVfLDa+3Xjtt
# TmIjx8oGdLB9BMrGMuHsOygfgi98eGbWQ2I5ZhzwBbJ7uFQdeTkMCswcAsVcj8pW
# e7/ixw2e+SYFm0q9Z/QiZZ7LFDp/b3u7/ufXCUBX2r1gi7Xi+x60E6dm3Ge3XAsY
# qSx9ZOlVNJlIs/ChP0KckHDMeFuCnRmNEvKC039syHWSy6VP8NO7fwwxK+XytyrK
# aJMyPS97kVXuqriKZIGsV0KjLOz3neh0OdQTolPv1R5yb9tI6Xc=
# =rtlE
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 10 Jul 2023 11:18:01 PM BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* tag 'mips-20230710' of https://github.com/philmd/qemu: (44 commits)
hw/ide/piix: Move registration of VMStateDescription to DeviceClass
hw/ide/pci: Replace some magic numbers by constants
hw/ide: Extract bmdma_status_writeb()
hw/ide: Extract IDEBus assignment into bmdma_init()
hw/isa/vt82c686: Remove via_isa_set_irq()
hw/ide/via: Wire up IDE legacy interrupts in host device
hw/ide/pci: Expose legacy interrupts as named GPIOs
target/mips: enable GINVx support for I6400 and I6500
target/mips/mxu: Add Q8SAD instruction
target/mips/mxu: Add S32SFL instruction
target/mips/mxu: Add Q8MADL instruction
target/mips/mxu: Add Q16SCOP instruction
target/mips/mxu: Add Q8MAC Q8MACSU instructions
target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions
target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions
target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions
target/mips/mxu: Add D32SLL D32SLR D32SAR instructions
target/mips/mxu: Add D32SARL D32SARW instructions
target/mips/mxu: Add S32ALN S32LUI insns
target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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target/mips: Implement Loongson CSR instructions

Loongson introduced CSR instructions since 3A4000, which looks
similar to IOCSR and CPUCFG instructions we seen in LoongArch.

Unfortunately we don't

target/mips: Implement Loongson CSR instructions

Loongson introduced CSR instructions since 3A4000, which looks
similar to IOCSR and CPUCFG instructions we seen in LoongArch.

Unfortunately we don't have much document about those instructions,
bit fields of CPUCFG instructions and IOCSR registers can be found
at 3A4000's user manual, while instruction encodings can be found
at arch/mips/include/asm/mach-loongson64/loongson_regs.h from
Linux Kernel.

Our predefined CPUCFG bits are differ from actual 3A4000, since
we can't emulate all CPUCFG features present in 3A4000 for now,
we just enable bits for what we have in TCG.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20230521214832.20145-2-jiaxun.yang@flygoat.com>
[JY: Fixed typo in ase_lcsr_available(),
retrict GEN_FALSE_TRANS]
[PMD: Fix meson's mips_softmmu_ss -> mips_system_ss,
restrict AddressSpace/MemoryRegion to SysEmu]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

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Merge tag 'pull-tcg-20230620' of https://gitlab.com/rth7680/qemu into staging

tcg: Define _CALL_AIX for clang on ppc64
accel/tcg: Build fix for macos catalina
accel/tcg: Handle MO_ATOM_WITHIN16 in d

Merge tag 'pull-tcg-20230620' of https://gitlab.com/rth7680/qemu into staging

tcg: Define _CALL_AIX for clang on ppc64
accel/tcg: Build fix for macos catalina
accel/tcg: Handle MO_ATOM_WITHIN16 in do_st16_leN
accel/tcg: Restrict SavedIOTLB to system emulation
accel/tcg: Use generic 'helper-proto-common.h' header
plugins: Remove unused 'exec/helper-proto.h' header
*: Check for CONFIG_USER_ONLY instead of CONFIG_SOFTMMU

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmSRYmIdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8zbAgAlX4GcShS1OU1BDRe
# b0HHHj1fFBB/9yk8f/5WuQb2snYS+pcZCez9XeT175ugovXSOz+shvmFrbRPvpfj
# q8C88CIKCJRsXnhWqKWOKDqgTttu2WNXOvCe0eCZbUoGQ9K1seMvUBq6T50fNv2H
# fXeHtLSu/+jiHIN3+woJqdgrkp0cko2rrpnwIpjuIsY1iz/J/VKEHmnv7Ah+GsRs
# OTYnR7iN6uhBXVll14r3UCylbgdEz58sSSEi3dYYfaTRuijDwOzM0evhk6+5XzHP
# DYwGdbtDE5HJOrCLiKegk80Gh6v1XVZQWnn9PdiN1eJcQsWNT9mYV9/4IsCVrsF4
# 8r5KUg==
# =JmjK
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 20 Jun 2023 10:25:06 AM CEST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20230620' of https://gitlab.com/rth7680/qemu:
cputlb: Restrict SavedIOTLB to system emulation
exec/cpu-defs: Check for SOFTMMU instead of !USER_ONLY
accel/tcg/cpu-exec: Use generic 'helper-proto-common.h' header
plugins: Remove unused 'exec/helper-proto.h' header
meson: Replace softmmu_ss -> system_ss
meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY
meson: Alias CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLY
accel/tcg: Check for USER_ONLY definition instead of SOFTMMU one
hw/core/cpu: Check for USER_ONLY definition instead of SOFTMMU one
target/ppc: Check for USER_ONLY definition instead of SOFTMMU one
target/m68k: Check for USER_ONLY definition instead of SOFTMMU one
target/tricore: Remove pointless CONFIG_SOFTMMU guard
target/i386: Simplify i386_tr_init_disas_context()
tcg/ppc: Define _CALL_AIX for clang on ppc64(be)
accel/tcg: Handle MO_ATOM_WITHIN16 in do_st16_leN
host/include/x86_64: Use __m128i for "x" constraints

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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meson: Replace softmmu_ss -> system_ss

We use the user_ss[] array to hold the user emulation sources,
and the softmmu_ss[] array to hold the system emulation ones.
Hold the latter in the 'system_ss[

meson: Replace softmmu_ss -> system_ss

We use the user_ss[] array to hold the user emulation sources,
and the softmmu_ss[] array to hold the system emulation ones.
Hold the latter in the 'system_ss[]' array for parity with user
emulation.

Mechanical change doing:

$ sed -i -e s/softmmu_ss/system_ss/g $(git grep -l softmmu_ss)

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230613133347.82210-10-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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Merge remote-tracking branch 'remotes/philmd/tags/mips-20210502' into staging

MIPS patches queue

- Fix CACHEE opcode
- Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes
- Remove isa_get_ir

Merge remote-tracking branch 'remotes/philmd/tags/mips-20210502' into staging

MIPS patches queue

- Fix CACHEE opcode
- Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes
- Remove isa_get_irq() call in PIIX4 south bridge
- Add various missing fields to the MIPS CPU migration vmstate
- Lot of code moved around to allow TCG or KVM only builds
- Restrict non-virtualized machines to TCG
- Add KVM mips64el cross-build jobs to gitlab-ci

# gpg: Signature made Sun 02 May 2021 15:56:51 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd/tags/mips-20210502: (36 commits)
gitlab-ci: Add KVM mips64el cross-build jobs
hw/mips: Restrict non-virtualized machines to TCG
target/mips: Move TCG source files under tcg/ sub directory
target/mips: Move CP0 helpers to sysemu/cp0.c
target/mips: Move exception management code to exception.c
target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c
target/mips: Move helper_cache() to tcg/sysemu/special_helper.c
target/mips: Move Special opcodes to tcg/sysemu/special_helper.c
target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope
target/mips: Move tlb_helper.c to tcg/sysemu/
target/mips: Restrict mmu_init() to TCG
target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder
target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG
target/mips: Move physical addressing code to sysemu/physaddr.c
target/mips: Move sysemu specific files under sysemu/ subfolder
target/mips: Move cpu_signal_handler definition around
target/mips: Add simple user-mode mips_cpu_tlb_fill()
target/mips: Add simple user-mode mips_cpu_do_interrupt()
target/mips: Introduce tcg-internal.h for TCG specific declarations
meson: Introduce meson_user_arch source set for arch-specific user-mode
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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target/mips: Move Special opcodes to tcg/sysemu/special_helper.c

Move the Special opcodes helpers to tcg/sysemu/special_helper.c.

Since mips_io_recompile_replay_branch() is set as
CPUClass::io_reco

target/mips: Move Special opcodes to tcg/sysemu/special_helper.c

Move the Special opcodes helpers to tcg/sysemu/special_helper.c.

Since mips_io_recompile_replay_branch() is set as
CPUClass::io_recompile_replay_branch handler in cpu.c,
we need to declare its prototype in "tcg-internal.h".

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-24-f4bug@amsat.org>

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target/mips: Move tlb_helper.c to tcg/sysemu/

Move tlb_helper.c to the tcg/sysemu/ subdir, along with
the following 3 declarations to tcg-internal.h:
- cpu_mips_tlb_flush()
- cpu_mips_translate_addr

target/mips: Move tlb_helper.c to tcg/sysemu/

Move tlb_helper.c to the tcg/sysemu/ subdir, along with
the following 3 declarations to tcg-internal.h:
- cpu_mips_tlb_flush()
- cpu_mips_translate_address()
- r4k_invalidate_tlb()

Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/
are only build when sysemu mode is configured.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-22-f4bug@amsat.org>

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target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder

Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder,
adapting the Meson machinery.

Move the opcode definitions to tcg

target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder

Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder,
adapting the Meson machinery.

Move the opcode definitions to tcg/sysemu_helper.h.inc.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-20-f4bug@amsat.org>

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