Merge tag 'mips-20221108' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Remove -Wclobbered in nanoMIPS disassembler (Richard Henderson)
- Fix invalid string formats in nanoMIP

Merge tag 'mips-20221108' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Remove -Wclobbered in nanoMIPS disassembler (Richard Henderson)
- Fix invalid string formats in nanoMIPS disassembler (myself)
- Allow Loongson-2F to access XKPHYS in kernel mode (Jiaxun Yang)
- Octeon opcode fixes (Jiaxun Yang, Pavel Dovgalyuk)
- MAINTAINERS nanoMIPS update

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# gpg: Signature made Mon 07 Nov 2022 19:05:10 EST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* tag 'mips-20221108' of https://github.com/philmd/qemu:
MAINTAINERS: Inherit from nanoMIPS
disas/nanomips: Tidy read for 48-bit opcodes
disas/nanomips: Split out read_u16
disas/nanomips: Merge insn{1,2,3} into words[3]
disas/nanomips: Move setjmp into nanomips_dis
disas/nanomips: Remove headers already included by "qemu/osdep.h"
disas/nanomips: Use G_GNUC_PRINTF to avoid invalid string formats
disas/nanomips: Fix invalid PRIx64 format calling img_format()
disas/nanomips: Fix invalid PRId64 format calling img_format()
target/mips: Don't check COP1X for 64 bit FP mode
target/mips: Disable DSP ASE for Octeon68XX
target/mips: Enable LBX/LWX/* instructions for Octeon
target/mips: Cast offset field of Octeon BBIT to int16_t
target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

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target/mips: Cast offset field of Octeon BBIT to int16_t

As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigne

target/mips: Cast offset field of Octeon BBIT to int16_t

As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference
Manual" offset field is signed 16 bit value. However arg_BBIT.offset
is unsigned. We need to cast it as signed to do address calculation.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20221031132531.18122-3-jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

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Merge tag 'mips-20220712' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Cavium Octeon MIPS extension and CPU model (Pavel Dovgalyuk)
- Semihosting cleanup (Richard Henderson)

Merge tag 'mips-20220712' of https://github.com/philmd/qemu into staging

MIPS patches queue

- Cavium Octeon MIPS extension and CPU model (Pavel Dovgalyuk)
- Semihosting cleanup (Richard Henderson)

# gpg: Signature made Tue 12 Jul 2022 21:52:52 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* tag 'mips-20220712' of https://github.com/philmd/qemu:
target/mips: Remove GET_TARGET_STRING and FREE_TARGET_STRING
target/mips: Simplify UHI_argnlen and UHI_argn
semihosting: Remove qemu_semihosting_log_out
target/mips: Use error_report for UHI_assert
target/mips: Avoid qemu_semihosting_log_out for UHI_plog
target/mips: Use semihosting/syscalls.h
target/mips: Drop link syscall from semihosting
target/mips: Create report_fault for semihosting
target/mips: introduce Cavium Octeon CPU model
target/mips: implement Octeon-specific arithmetic instructions
target/mips: implement Octeon-specific BBIT instructions
target/mips: introduce decodetree structure for Cavium Octeon extension

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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target/mips: implement Octeon-specific arithmetic instructions

This patch implements several Octeon-specific instructions:
- BADDU
- DMUL
- EXTS/EXTS32
- CINS/CINS32
- POP/DPOP
- SEQ/SEQI
- SNE/SNEI

target/mips: implement Octeon-specific arithmetic instructions

This patch implements several Octeon-specific instructions:
- BADDU
- DMUL
- EXTS/EXTS32
- CINS/CINS32
- POP/DPOP
- SEQ/SEQI
- SNE/SNEI

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165572673245.167724.17377788816335619000.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

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target/mips: implement Octeon-specific BBIT instructions

This patch introduces Octeon-specific decoder and implements
check-bit-and-jump instructions.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyu

target/mips: implement Octeon-specific BBIT instructions

This patch introduces Octeon-specific decoder and implements
check-bit-and-jump instructions.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165572672705.167724.16667636081912075906.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

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target/mips: introduce decodetree structure for Cavium Octeon extension

This patch adds decodetree for Cavium Octeon extension and
an instruction set extension flag for using it in CPU models.

Sign

target/mips: introduce decodetree structure for Cavium Octeon extension

This patch adds decodetree for Cavium Octeon extension and
an instruction set extension flag for using it in CPU models.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

show more ...