Merge tag 'pull-hex-20240505' of https://github.com/quic/qemu into staging

Short-circuit for packets with r/w and no overlap

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Merge tag 'pull-hex-20240505' of https://github.com/quic/qemu into staging

Short-circuit for packets with r/w and no overlap

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# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 05 May 2024 04:24:15 PM PDT
# gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# gpg: aka "Brian Cain <bcain@kernel.org>" [unknown]
# gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown]
# gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown]
# gpg: aka "bcain" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47
# Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32

* tag 'pull-hex-20240505' of https://github.com/quic/qemu:
Hexagon (target/hexagon) Remove hex_common.read_attribs_file
Hexagon (target/hexagon) Remove gen_shortcode.py
Hexagon (target/hexagon) Remove gen_op_regs.py
Hexagon (target/hexagon) Remove uses of op_regs_generated.h.inc
Hexagon (tests/tcg/hexagon) Test HVX .new read from high half of pair
Hexagon (target/hexagon) Mark has_pred_dest in trans functions
Hexagon (target/hexagon) Mark dest_idx in trans functions
Hexagon (target/hexagon) Mark new_read_idx in trans functions
Hexagon (target/hexagon) Add is_old/is_new to Register class
Hexagon (target/hexagon) Only pass env to generated helper when needed
Hexagon (target/hexagon) Pass SP explicitly to helpers that need it
Hexagon (target/hexagon) Pass P0 explicitly to helpers that need it
Hexagon (target/hexagon) Enable more short-circuit packets (HVX)
Hexagon (target/hexagon) Enable more short-circuit packets (scalar core)
Hexagon (target/hexagon) Analyze reads before writes

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Hexagon (target/hexagon) Remove hex_common.read_attribs_file

The attribinfo data structure is not used
Adjust the command-line arguments to the python scripts
Add hex_common.read_common_files for TC

Hexagon (target/hexagon) Remove hex_common.read_attribs_file

The attribinfo data structure is not used
Adjust the command-line arguments to the python scripts
Add hex_common.read_common_files for TCG/helper generation scripts

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240307032327.4799-10-ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>

show more ...

Hexagon (target/hexagon) Enable more short-circuit packets (HVX)

Look for read-after-write instead of overlap of reads and writes

HVX instructions with helpers have pass-by-reference semantics, so

Hexagon (target/hexagon) Enable more short-circuit packets (HVX)

Look for read-after-write instead of overlap of reads and writes

HVX instructions with helpers have pass-by-reference semantics, so
we check for overlaps of reads and writes within the same instruction.

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20240201103340.119081-4-ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>

show more ...

Hexagon (target/hexagon) Analyze reads before writes

We divide gen_analyze_funcs.py into 3 phases
Declare the operands
Analyze the register reads
Analyze the register writes

We also cre

Hexagon (target/hexagon) Analyze reads before writes

We divide gen_analyze_funcs.py into 3 phases
Declare the operands
Analyze the register reads
Analyze the register writes

We also create special versions of ctx_log_*_read for new operands
Check that the operand is written before the read

This is a precursor to improving the analysis for short-circuiting
the packet semantics in a subsequent commit

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20240201103340.119081-2-ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>

show more ...

Merge tag 'pull-hex-20240121' of https://github.com/quic/qemu into staging

Coverity fix, cross toolchain update, switch to decodetree

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Merge tag 'pull-hex-20240121' of https://github.com/quic/qemu into staging

Coverity fix, cross toolchain update, switch to decodetree

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# =aIh2
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 22 Jan 2024 06:03:40 GMT
# gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain <bcain@kernel.org>" [full]
# gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [full]
# gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [full]
# gpg: aka "bcain" [full]
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47
# Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32

* tag 'pull-hex-20240121' of https://github.com/quic/qemu:
target/hexagon: reduce scope of def_regnum, remove dead assignment
Hexagon (target/hexagon) Remove old dectree.py
Hexagon (target/hexagon) Use QEMU decodetree (16-bit instructions)
Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions)
Hexagon (target/hexagon) Remove dead functions from hex_common.py
Hexagon (target/hexagon) Remove unused WRITES_PRED_REG attribute
Hexagon (target/hexagon) Make generators object oriented - gen_analyze_funcs
Hexagon (target/hexagon) Make generators object oriented - gen_op_regs
Hexagon (target/hexagon) Make generators object oriented - gen_idef_parser_funcs
Hexagon (target/hexagon) Make generators object oriented - gen_helper_funcs
Hexagon (target/hexagon) Make generators object oriented - gen_helper_protos
Hexagon (target/hexagon) Make generators object oriented - gen_tcg_funcs
Hexagon (target/hexagon) Clean up handling of modifier registers
Hexagon (target/hexagon) Fix shadow variable when idef-parser is off
tests/docker: Hexagon toolchain update

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Hexagon (target/hexagon) Make generators object oriented - gen_analyze_funcs

This patch conflicts with
https://lists.gnu.org/archive/html/qemu-devel/2023-11/msg00729.html
If that series goes in firs

Hexagon (target/hexagon) Make generators object oriented - gen_analyze_funcs

This patch conflicts with
https://lists.gnu.org/archive/html/qemu-devel/2023-11/msg00729.html
If that series goes in first, we'll rework this patch and vice versa.

Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Message-Id: <20231210220712.491494-8-ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>

show more ...

Merge tag 'pull-hex-20230526' of https://github.com/quic/qemu into staging

Hexagon update

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Merge tag 'pull-hex-20230526' of https://github.com/quic/qemu into staging

Hexagon update

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# gpg: Signature made Fri 26 May 2023 07:18:12 AM PDT
# gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422

* tag 'pull-hex-20230526' of https://github.com/quic/qemu:
Hexagon (target/hexagon) Change Hexagon maintainer
Hexagon: fix outdated `hex_new_*` comments
target/hexagon/*.py: clean up used 'toss' and 'numregs' vars
Hexagon (target/hexagon) Fix assignment to tmp registers
Hexagon (tests/tcg/hexagon) Clean up Hexagon check-tcg tests

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/hexagon/*.py: clean up used 'toss' and 'numregs' vars

Many Hexagon python scripts call hex_common.get_tagregs(), but only one
call site use the full reg structure given by this function. To m

target/hexagon/*.py: clean up used 'toss' and 'numregs' vars

Many Hexagon python scripts call hex_common.get_tagregs(), but only one
call site use the full reg structure given by this function. To make the
code cleaner, let's make get_tagregs() filter out the unused fields
(i.e. 'toss' and 'numregs'), properly removed the unused variables at
the call sites. The hex_common.bad_register() function is also adjusted
to work exclusively with 'regtype' and 'regid' args. For the single call
site that does use toss/numregs, we provide an optional parameter to
get_tagregs() which will restore the old full behavior.

Suggested-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <3ffd4ccb972879f57f499705c624e8eaba7f8b52.1684939078.git.quic_mathbern@quicinc.com>

show more ...

Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into staging

Hexagon update

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Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into staging

Hexagon update

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# gpg: Signature made Thu 18 May 2023 12:48:24 PM PDT
# gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422

* tag 'pull-hex-20230518-1' of https://github.com/quic/qemu: (44 commits)
Hexagon (linux-user/hexagon): handle breakpoints
Hexagon (gdbstub): add HVX support
Hexagon (gdbstub): fix p3:0 read and write via stub
Hexagon: add core gdbstub xml data for LLDB
gdbstub: add test for untimely stop-reply packets
gdbstub: only send stop-reply packets when allowed to
Remove test_vshuff from hvx_misc tests
Hexagon (decode): look for pkts with multiple insns at the same slot
Hexagon (iclass): update J4_hintjumpr slot constraints
Hexagon: append eflags to unknown cpu model string
Hexagon: list available CPUs with `-cpu help`
Hexagon (target/hexagon/*.py): raise exception on reg parsing error
target/hexagon: fix = vs. == mishap
Hexagon (target/hexagon) Additional instructions handled by idef-parser
Hexagon (target/hexagon) Move items to DisasContext
Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext
Hexagon (target/hexagon) Move pred_written to DisasContext
Hexagon (target/hexagon) Move new_pred_value to DisasContext
Hexagon (target/hexagon) Move new_value to DisasContext
Hexagon (target/hexagon) Make special new_value for USR
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Hexagon (target/hexagon/*.py): raise exception on reg parsing error

Currently, the python scripts used for the hexagon building will not
abort the compilation when there is an error parsing a regist

Hexagon (target/hexagon/*.py): raise exception on reg parsing error

Currently, the python scripts used for the hexagon building will not
abort the compilation when there is an error parsing a register. Let's
make the compilation properly fail in such cases by rasing an exception
instead of just printing a warning message, which might get lost in the
output.

This patch was generated with:

git grep -l "Bad register" *hexagon* | \
xargs sed -i "" -e 's/print("Bad register parse: "[, ]*\([^)]*\))/hex_common.bad_register(\1)/g'

Plus the bad_register() helper added to hex_common.py.

Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <1f5dbd92f68fdd89e2647e4ba527a2c32cf0f070.1683217043.git.quic_mathbern@quicinc.com>

show more ...

Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext

The pkt_has_store_s1 field is only used for bookkeeping helpers with
a load. With recent changes that eliminate the need to free TCGv

Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext

The pkt_has_store_s1 field is only used for bookkeeping helpers with
a load. With recent changes that eliminate the need to free TCGv
variables, it makes more sense to make this transient.

These helpers already take the instruction slot as an argument. We
combine the slot and pkt_has_store_s1 into a single argument called
slotval.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-21-tsimpson@quicinc.com>

show more ...

Hexagon (target/hexagon) Short-circuit more HVX single instruction packets

The generated helpers for HVX use pass-by-reference, so they can't
short-circuit when the reads/writes overlap. The instru

Hexagon (target/hexagon) Short-circuit more HVX single instruction packets

The generated helpers for HVX use pass-by-reference, so they can't
short-circuit when the reads/writes overlap. The instructions with
overrides are OK because they use tcg_gen_gvec_*.

We add a flag has_hvx_helper to DisasContext and extend gen_analyze_funcs
to set the flag when the instruction is an HVX instruction with a
generated helper.

We add an override for V6_vcombine so that it can be short-circuited
along with a test case in tests/tcg/hexagon/hvx_misc.c

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-15-tsimpson@quicinc.com>

show more ...

Hexagon (target/hexagon) Mark registers as read during packet analysis

Have gen_analyze_funcs mark the registers that are read by the
instruction. We also mark the implicit reads using instruction

Hexagon (target/hexagon) Mark registers as read during packet analysis

Have gen_analyze_funcs mark the registers that are read by the
instruction. We also mark the implicit reads using instruction
attributes.

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-11-tsimpson@quicinc.com>

show more ...

Merge tag 'pull-hex-20230421' of https://github.com/quic/qemu into staging

Hexagon update

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Merge tag 'pull-hex-20230421' of https://github.com/quic/qemu into staging

Hexagon update

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# gpg: Signature made Fri 21 Apr 2023 05:38:16 PM BST
# gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422

* tag 'pull-hex-20230421' of https://github.com/quic/qemu:
Hexagon (target/hexagon) Add overrides for cache/sync/barrier instructions
Hexagon (target/hexagon) Remove unused slot variable in helpers
Hexagon (tests/tcg/hexagon) Move HVX test infra to header file
Hexagon (target/hexagon) Updates to USR should use get_result_gpr
Hexagon (target/hexagon) Add overrides for count trailing zeros/ones
Hexagon (target/hexagon) Merge arguments to probe_pkt_scalar_hvx_stores
Hexagon (target/hexagon) Remove redundant/unused macros
Use black code style for python scripts
Use f-strings in python scripts
Hexagon (translate.c): avoid redundant PC updates on COF

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Use black code style for python scripts

Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Acked-by: Taylor Simpson <tsimpson@quicinc.com>
Te

Use black code style for python scripts

Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Acked-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20230320092533.2859433-3-quic_mliebel@quicinc.com>

show more ...

Use f-strings in python scripts

Replace python 2 format string with f-strings

Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by

Use f-strings in python scripts

Replace python 2 format string with f-strings

Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Tested-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20230320092533.2859433-2-quic_mliebel@quicinc.com>

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Merge tag 'pull-hex-20230306' of https://github.com/quic/qemu into staging

Hexagon (target/hexagon) update

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Merge tag 'pull-hex-20230306' of https://github.com/quic/qemu into staging

Hexagon (target/hexagon) update

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* tag 'pull-hex-20230306' of https://github.com/quic/qemu:
Hexagon (target/hexagon) Improve code gen for predicated HVX instructions
Hexagon (target/hexagon) Reduce manipulation of slot_cancelled
Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]
Hexagon (target/hexagon) Change subtract from zero to change sign
Hexagon (tests/tcg/hexagon) Enable HVX tests
Hexagon (tests/tcg/hexagon) Remove __builtin from scatter_gather
Hexagon (tests/tcg/hexagon) Update preg_alias.c
Hexagon (target/hexagon) Analyze packet for HVX
Hexagon (target/hexagon) Don't set pkt_has_store_s1 when not needed
Hexagon (target/hexagon) Analyze packet before generating TCG
Hexagon (target/hexagon) Add overrides for dealloc-return instructions
Hexagon (target/hexagon) Add overrides for endloop1/endloop01
Hexagon (target/hexagon) Add overrides for callr
Hexagon (target/hexagon) Add overrides for jumpr31 instructions
target/hexagon/idef-parser: Remove unused code paths
target/hexagon/idef-parser: Elide mov in gen_pred_assign
Hexagon (target/hexagon) Restore --disable-hexagon-idef-parser build

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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Hexagon (target/hexagon) Improve code gen for predicated HVX instructions

The following improvements are made for predicated HVX instructions
During gen_commit_hvx, unconditionally move the "new

Hexagon (target/hexagon) Improve code gen for predicated HVX instructions

The following improvements are made for predicated HVX instructions
During gen_commit_hvx, unconditionally move the "new" value into
the dest
Don't set slot_cancelled
Remove runtime bookkeeping of which registers were updated
Reduce the cases where gen_log_vreg_write[_pair] is called
It's only needed for special operands VxxV and VyV
Remove gen_log_qreg_write

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-15-tsimpson@quicinc.com>

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Hexagon (target/hexagon) Analyze packet for HVX

Extend the analyze_<tag> functions for HVX vector and predicate writes
Remove calls to ctx_log_vreg_write[_pair] from gen_tcg_funcs.py
During gen_star

Hexagon (target/hexagon) Analyze packet for HVX

Extend the analyze_<tag> functions for HVX vector and predicate writes
Remove calls to ctx_log_vreg_write[_pair] from gen_tcg_funcs.py
During gen_start_packet, reload the predicated HVX registers into
fugure_VRegs and tmp_VRegs

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-8-tsimpson@quicinc.com>

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Hexagon (target/hexagon) Don't set pkt_has_store_s1 when not needed

The pkt_has_store_s1 field in CPUHexagonState is only needed in generated
helpers for scalar load instructions. See check_noshuf

Hexagon (target/hexagon) Don't set pkt_has_store_s1 when not needed

The pkt_has_store_s1 field in CPUHexagonState is only needed in generated
helpers for scalar load instructions. See check_noshuf and mem_load[1248]
in op_helper.c.

We add logic in gen_analyze_funcs.py to set need_pkt_has_store_s1 in
DisasContext when it is needed at runtime.

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-7-tsimpson@quicinc.com>

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Hexagon (target/hexagon) Analyze packet before generating TCG

We create a new generator that creates an analyze_<tag> function for
each instruction. Currently, these functions record the writes to

Hexagon (target/hexagon) Analyze packet before generating TCG

We create a new generator that creates an analyze_<tag> function for
each instruction. Currently, these functions record the writes to
R, P, and C registers by calling ctx_log_reg_write[_pair] or
ctx_log_pred_write.

During gen_start_packet, we invoke the analyze_<tag> function for
each instruction in the packet, and we mark the implicit register
and predicate writes.

Doing the analysis up front has several advantages
- We remove calls to ctx_log_* from gen_tcg_funcs.py and genptr.c
- After the analysis is performed, we can initialize hex_new_value
for each of the predicated assignments rather than during TCG
generation for the instructions
- This is a stepping stone for future work where the analysis will
include the set of registers that are read. In cases where
the packet doesn't have an overlap between the registers that are
written and registers that are read, we can avoid the intermediate
step of writing to hex_new_value. Note that other checks will also
be needed (e.g., no instructions can raise an exception).

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-6-tsimpson@quicinc.com>

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