Merge tag 'single-binary-20241015' of https://github.com/philmd/qemu into staging

Remove some target-specific endianness knowledge from target/.

For MIPS, propagate endianness at the board level, u

Merge tag 'single-binary-20241015' of https://github.com/philmd/qemu into staging

Remove some target-specific endianness knowledge from target/.

For MIPS, propagate endianness at the board level, using QOM property.

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmcOihcACgkQ4+MsLN6t
# wN4VaRAAor+5gUJiV0OOMQVfP8e1o9ssKcYy9m31zLeii1Iq2M/2oz6YK4OjdQDe
# oJ8VRJvBPKC2Bpi14TfKsSGaP8CGNO/hdxcMi71pjHZC+bjHt5Uv0U/7T4XCBWuV
# N+85juN1PTc4cci4FkGIXaPB1YWL00L56BDCzja0uhLF4+Xe2eYGVrPXeFCkN/3I
# Ky7jHlB/dgzc47kTXvg5snCee2egDFf/x4igwZj6+gWJyo+jubRpwoOqKbK2M0Nd
# VvNpBVFNGZMP3Fn9lh45uDOuRWGu6zSIPBVkjoFc+wdGsFsITIMrZ3h46UffsGTJ
# F1j6Zsq6hoLbaNRRjZ6OsN6u683oo1lknmWauD62LrjXcX0RlRwRFbMD0AjedR8t
# 6+YHg5LlwGg6r/AOtEe28ggXZohB2vjr2V0MJm1x/XgLYhFHoN3//jxn22oOHj4p
# 0z3+eDc3Se8JNRV6jPMHbbuTqZqZjRgVFbYN3aMbdoXYzhpYnrPj6f7WQL2smiAW
# C2vdswrubQWKou1wcn6rbg0nnMRVTh+GxrtZ3mkgaxNzgNFxsrX8YubMsh77XUcr
# mnCGj1tE3hp40xsuSk6yZXY3ZZiTyZasvO1wq4gWOI9le0Zmq+d335F9+IVJ8RlP
# YhA+MY5aeomsixVRdmrPrgOfanQiHXv02lsbperU8QFfGRhf2Y8=
# =Qydb
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 15 Oct 2024 16:28:23 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* tag 'single-binary-20241015' of https://github.com/philmd/qemu: (33 commits)
hw/mips: Have mips_cpu_create_with_clock() take an endianness argument
hw/mips/cps: Set the vCPU 'cpu-big-endian' property
target/mips: Expose MIPSCPU::is_big_endian property
target/mips: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
target/mips: Use gen_op_addr_addi() when possible
target/mips: Have gen_addiupc() expand $pc during translation
target/mips: Replace MO_TE by mo_endian()
target/mips: Introduce mo_endian() helper
target/mips: Remove unused MEMOP_IDX() macro
target/mips: Rename unused sysemu argument of OP_LD_ATOMIC()
target/mips: Explode MO_TExx -> MO_TE | MO_xx
target/mips: Factor mo_endian_rev() out of MXU code
target/mips: Convert mips16e decr_and_load/store() macros to functions
target/mips: Replace MO_TE by mo_endian_env() in get_pte()
target/mips: Introduce mo_endian_env() helper
target/mips: Rename cpu_is_bigendian() -> disas_is_bigendian()
target/mips: Declare mips_env_is_bigendian() in 'internal.h'
hw/xtensa/xtfpga: Remove TARGET_BIG_ENDIAN #ifdef'ry
target/ppc: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
target/tricore: Use tcg_constant_tl() instead of tcg_gen_movi_tl()
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/avr: Use explicit little-endian LD/ST API

The AVR architecture uses little endianness. Directly use
the little-endian LD/ST API.

Mechanical change using:

$ end=le; \
for acc in uw w l

target/avr: Use explicit little-endian LD/ST API

The AVR architecture uses little endianness. Directly use
the little-endian LD/ST API.

Mechanical change using:

$ end=le; \
for acc in uw w l q tul; do \
sed -i -e "s/ld${acc}_p(/ld${acc}_${end}_p(/" \
-e "s/st${acc}_p(/st${acc}_${end}_p(/" \
$(git grep -wlE '(ld|st)t?u?[wlq]_p' target/avr/); \
done

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20241004163042.85922-11-philmd@linaro.org>

show more ...

Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging

Accelerators patches

A lot of trivial cleanups and simplifications (moving methods around,
adding/removing #include stateme

Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging

Accelerators patches

A lot of trivial cleanups and simplifications (moving methods around,
adding/removing #include statements). Most notable changes:

- Rename NEED_CPU_H -> COMPILING_PER_TARGET
- Rename few template headers using the '.h.inc' suffix
- Extract some definitions / declarations into their own header:
- accel/tcg/user-retaddr.h (helper_retaddr)
- include/exec/abi_ptr.h (abi_ptr)
- include/exec/breakpoint.h (CPUBreakpoint, CPUWatchpoint)
- include/exec/mmu-access-type.h (MMUAccessType)
- include/user/tswap-target.h (tswapl, bswaptls)

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmYsAuEACgkQ4+MsLN6t
# wN78Rg//V9UoE0U9Lh6Sd2WpcSAYP9D1CBa+iGXhrmel0utER1sQLu022nvcLdHc
# XtCgtX3H0yECF8dPX02rVp8IbSlOv3c8N/a6BxD79cRGqgXBYR/dEUqfXqeLJn3l
# a58YU3i7sLNQ0l7VnwTiBnI0lw170/xJl2B2mcR1SvWuH3dr5vTeIXNureu36ORo
# rc0oqWHbw1Pyyn8ADE2kPyFCOiwPwvcOvAk8dXGfib+mNCwNVV+ZUtAPi711VD8d
# 9VW2gu2sXwnWdpROrSugSw+aPVF4UjltL9qJEl5bxoqWFmlET1Zn2NpKvsocUXmh
# CMQQS2Tr4LpaaVQJGxx0yUe0B65X5+gCkIhsMOubED7GRyTCjrkOPm6exz3ge6WV
# YmIboggFAk3OjAzLs7yZVkWsTK1Y3+3eX0u7AWPUsUu7rCT/Toc6QxDS7eT2hJfq
# UDXI355PGbImgiArQa+OsT7v1Le4/iQa+TfN4fdUDpxEdfaxhnijWh+E91CEp+w/
# Mq7db9Z1aMnhFKIKdkPYyfwB74yXQrmYchJ0QojZjbzqNGwkt9VeC7O9RcYjEaHM
# hMIexwccxexqGH22wn8vPd6ZVKtiLaG4AXO0v6Dn2YJ7/zb/ntcI6lRZqdBAHKNK
# MzkjTRRRR0wAfu8Lk8CaNNEqUP4Po43fbYymo6AZhIR8NqfApL0=
# =ifBx
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 26 Apr 2024 12:39:13 PM PDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* tag 'accel-20240426' of https://github.com/philmd/qemu: (38 commits)
plugins: Include missing 'qemu/bitmap.h' header
hw/core: Avoid including the full 'hw/core/cpu.h' in 'tcg-cpu-ops.h'
exec: Move CPUTLBEntry helpers to cputlb.c
exec: Restrict inclusion of 'user/guest-base.h'
exec: Rename 'exec/user/guest-base.h' as 'user/guest-base.h'
exec: Restrict 'cpu_ldst.h' to TCG accelerator
exec: Restrict TCG specific declarations of 'cputlb.h'
exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header
exec: Declare MMUAccessType type in 'mmu-access-type.h' header
exec: Declare abi_ptr type in its own 'abi_ptr.h' header
exec/user: Do not include 'cpu.h' in 'abitypes.h'
exec: Move [b]tswapl() declarations to 'exec/user/tswap-target.h'
exec: Declare target_words_bigendian() in 'exec/tswap.h'
exec/cpu-all: Remove unused tswapls() definitions
exec/cpu-all: Remove unused 'qemu/thread.h' header
exec/cpu-all: Reduce 'qemu/rcu.h' header inclusion
accel/hvf: Use accel-specific per-vcpu @dirty field
accel/nvmm: Use accel-specific per-vcpu @dirty field
accel/whpx: Use accel-specific per-vcpu @dirty field
accel/tcg: Rename helper-head.h -> helper-head.h.inc
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

gdbstub: Avoid including 'cpu.h' in 'gdbstub/helpers.h'

We only need the "exec/tswap.h" and "cpu-param.h" headers.
Only include "cpu.h" in the target gdbstub.c source files.

Signed-off-by: Philippe

gdbstub: Avoid including 'cpu.h' in 'gdbstub/helpers.h'

We only need the "exec/tswap.h" and "cpu-param.h" headers.
Only include "cpu.h" in the target gdbstub.c source files.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240418192525.97451-20-philmd@linaro.org>

show more ...

Merge tag 'pull-request-2024-03-12' of https://gitlab.com/thuth/qemu into staging

* Add missing ERRP_GUARD() statements in functions that need it
* Prefer fast cpu_env() over slower CPU QOM cast mac

Merge tag 'pull-request-2024-03-12' of https://gitlab.com/thuth/qemu into staging

* Add missing ERRP_GUARD() statements in functions that need it
* Prefer fast cpu_env() over slower CPU QOM cast macro

# -----BEGIN PGP SIGNATURE-----
#
# iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmXwPhYRHHRodXRoQHJl
# ZGhhdC5jb20ACgkQLtnXdP5wLbWHvBAAgKx5LHFjz3xREVA+LkDTQ49mz0lK3s32
# SGvNlIHjiaDGVttVYhVC4sinBWUruG4Lyv/2QN72OJBzn6WUsEUQE3KPH1d7Y3/s
# wS9X7mj70n4kugWJqeIJP5AXSRasHmWoQ4QJLVQRJd6+Eb9jqwep0x7bYkI1de6D
# bL1Q7bIfkFeNQBXaiPWAm2i+hqmT4C1r8HEAGZIjAsMFrjy/hzBEjNV+pnh6ZSq9
# Vp8BsPWRfLU2XHm4WX0o8d89WUMAfUGbVkddEl/XjIHDrUD+Zbd1HAhLyfhsmrnE
# jXIwSzm+ML1KX4MoF5ilGtg8Oo0gQDEBy9/xck6G0HCm9lIoLKlgTxK9glr2vdT8
# yxZmrM9Hder7F9hKKxmb127xgU6AmL7rYmVqsoQMNAq22D6Xr4UDpgFRXNk2/wO6
# zZZBkfZ4H4MpZXbd/KJpXvYH5mQA4IpkOy8LJdE+dbcHX7Szy9ksZdPA+Z10hqqf
# zqS13qTs3abxymy2Q/tO3hPKSJCk1+vCGUkN60Wm+9VoLWGoU43qMc7gnY/pCS7m
# 0rFKtvfwFHhokX1orK0lP/ppVzPv/5oFIeK8YDY9if+N+dU2LCwVZHIuf2/VJPRq
# wmgH2vAn3JDoRKPxTGX9ly6AMxuZaeP92qBTOPap0gDhihYzIpaCq9ecEBoTakI7
# tdFhV0iRr08=
# =NiP4
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 12 Mar 2024 11:35:50 GMT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2024-03-12' of https://gitlab.com/thuth/qemu: (55 commits)
user: Prefer fast cpu_env() over slower CPU QOM cast macro
target/xtensa: Prefer fast cpu_env() over slower CPU QOM cast macro
target/tricore: Prefer fast cpu_env() over slower CPU QOM cast macro
target/sparc: Prefer fast cpu_env() over slower CPU QOM cast macro
target/sh4: Prefer fast cpu_env() over slower CPU QOM cast macro
target/rx: Prefer fast cpu_env() over slower CPU QOM cast macro
target/ppc: Prefer fast cpu_env() over slower CPU QOM cast macro
target/openrisc: Prefer fast cpu_env() over slower CPU QOM cast macro
target/nios2: Prefer fast cpu_env() over slower CPU QOM cast macro
target/mips: Prefer fast cpu_env() over slower CPU QOM cast macro
target/microblaze: Prefer fast cpu_env() over slower CPU QOM cast macro
target/m68k: Prefer fast cpu_env() over slower CPU QOM cast macro
target/loongarch: Prefer fast cpu_env() over slower CPU QOM cast macro
target/i386/hvf: Use CPUState typedef
target/hexagon: Prefer fast cpu_env() over slower CPU QOM cast macro
target/cris: Prefer fast cpu_env() over slower CPU QOM cast macro
target/avr: Prefer fast cpu_env() over slower CPU QOM cast macro
target/alpha: Prefer fast cpu_env() over slower CPU QOM cast macro
target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handler
bulk: Call in place single use cpu_env()
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/avr: Prefer fast cpu_env() over slower CPU QOM cast macro

Mechanical patch produced running the command documented
in scripts/coccinelle/cpu_env.cocci_template header.

Reviewed-by: Richard H

target/avr: Prefer fast cpu_env() over slower CPU QOM cast macro

Mechanical patch produced running the command documented
in scripts/coccinelle/cpu_env.cocci_template header.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240129164514.73104-10-philmd@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

Merge tag 'pull-gdbstub-070323-3' of https://gitlab.com/stsquad/qemu into staging

gdbstub refactor:

- split user and softmmu code
- use cleaner headers for tb_flush, target_ulong
- probe for

Merge tag 'pull-gdbstub-070323-3' of https://gitlab.com/stsquad/qemu into staging

gdbstub refactor:

- split user and softmmu code
- use cleaner headers for tb_flush, target_ulong
- probe for gdb multiarch support at configure
- make syscall handling target independent
- add update guest debug of accel ops

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmQHomMACgkQ+9DbCVqe
# KkTtFAf/aEyKY0iUNxtB4/oV1L2VnLaZi+iKoZT4RQgrhOhzr5WV6/3/V05cw1RJ
# SIwcl8wB4gowYILs44eM/Qzcixiugl++2rvM4YVXiQyWKzkH6sY4X2iFuPGTwHLp
# y+E7RM77QNS7M9xYaVkdsQawnbsgjG67wZKbb88aaekFEn61UuDg1V2Nqa2ICy7Y
# /8yGIB2ixDfXOF0z4g8NOG44BXTDBtJbcEzf5GMz6D4HGnPZUbENy1nT0OcBk3zK
# PqKPNkPFZ360pqA9MtougjZ3xTBb7Afe9nRRMquV2RoFmkkY2otSjdPBFQu5GBlm
# NyTXEzjIQ6tCZlbS0eqdPVrUHHUx9g==
# =Al36
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Mar 2023 20:45:23 GMT
# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44

* tag 'pull-gdbstub-070323-3' of https://gitlab.com/stsquad/qemu: (30 commits)
gdbstub: move update guest debug to accel ops
gdbstub: Build syscall.c once
stubs: split semihosting_get_target from system only stubs
gdbstub: Adjust gdb_do_syscall to only use uint32_t and uint64_t
gdbstub: Remove gdb_do_syscallv
gdbstub: split out softmmu/user specifics for syscall handling
include: split target_long definition from cpu-defs
testing: probe gdb for supported architectures ahead of time
gdbstub: only compile gdbstub twice for whole build
gdbstub: move syscall handling to new file
gdbstub: move register helpers into standalone include
gdbstub: don't use target_ulong while handling registers
gdbstub: fix address type of gdb_set_cpu_pc
gdbstub: specialise stub_can_reverse
gdbstub: introduce gdb_get_max_cpus
gdbstub: specialise target_memory_rw_debug
gdbstub: specialise handle_query_attached
gdbstub: abstract target specific details from gdb_put_packet_binary
gdbstub: rationalise signal mapping in softmmu
gdbstub: move chunks of user code into own files
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

gdbstub: move register helpers into standalone include

These inline helpers are all used by target specific code so move them
out of the general header so we don't needlessly pollute the rest of
the

gdbstub: move register helpers into standalone include

These inline helpers are all used by target specific code so move them
out of the general header so we don't needlessly pollute the rest of
the API with target specific stuff.

Note we have to include cpu.h in semihosting as it was relying on a
side effect before.

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

Message-Id: <20230302190846.2593720-21-alex.bennee@linaro.org>
Message-Id: <20230303025805.625589-21-richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210721' into staging

Atomic build fixes for clang-12
Breakpoint reorg

# gpg: Signature made Wed 21 Jul 2021 20:57:50 BST
# gpg:

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210721' into staging

Atomic build fixes for clang-12
Breakpoint reorg

# gpg: Signature made Wed 21 Jul 2021 20:57:50 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210721: (27 commits)
accel/tcg: Record singlestep_enabled in tb->cflags
accel/tcg: Hoist tb_cflags to a local in translator_loop
accel/tcg: Remove TranslatorOps.breakpoint_check
accel/tcg: Move breakpoint recognition outside translation
accel/tcg: Merge tb_find into its only caller
target/avr: Implement gdb_adjust_breakpoint
hw/core: Introduce CPUClass.gdb_adjust_breakpoint
target/i386: Implement debug_check_breakpoint
target/arm: Implement debug_check_breakpoint
hw/core: Introduce TCGCPUOps.debug_check_breakpoint
accel/tcg: Use CF_NO_GOTO_{TB, PTR} in cpu_exec_step_atomic
accel/tcg: Handle -singlestep in curr_cflags
accel/tcg: Drop CF_NO_GOTO_PTR from -d nochain
accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTR
target/alpha: Drop goto_tb path in gen_call_pal
accel/tcg: Move curr_cflags into cpu-exec.c
accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNS
accel/tcg: Push trace info building into atomic_common.c.inc
trace: Fold mem-internal.h into mem.h
accel/tcg: Expand ATOMIC_MMU_LOOKUP_*
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/avr: Implement gdb_adjust_breakpoint

Ensure at registration that all breakpoints are in
code space, not data space.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richa

target/avr: Implement gdb_adjust_breakpoint

Ensure at registration that all breakpoints are in
code space, not data space.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/avr-port-20200711' into staging

8bit AVR port from Michael Rolnik.

Michael started to work on the AVR port few years ago [*] and kept
improv

Merge remote-tracking branch 'remotes/philmd-gitlab/tags/avr-port-20200711' into staging

8bit AVR port from Michael Rolnik.

Michael started to work on the AVR port few years ago [*] and kept
improving the code over various series.

List of people who help him (in chronological order):
- Richard Henderson
- Sarah Harris and Edward Robbins
- Philippe Mathieu-Daudé and Aleksandar Markovic
- Pavel Dovgalyuk
- Thomas Huth

[*] The oldest contribution I could find on the list is from 2016:
https://lists.nongnu.org/archive/html/qemu-devel/2016-06/msg02985.html

Tests included:

$ avocado --show=app run -t arch:avr tests/acceptance/
Fetching asset from tests/acceptance/machine_avr6.py:AVR6Machine.test_freertos
(1/1) tests/acceptance/machine_avr6.py:AVR6Machine.test_freertos: PASS (2.13 s)
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
JOB TIME : 2.35 s

$ make check-qtest-avr
TEST check-qtest-avr: tests/qtest/boot-serial-test
TEST check-qtest-avr: tests/qtest/cdrom-test
TEST check-qtest-avr: tests/qtest/device-introspect-test
TEST check-qtest-avr: tests/qtest/machine-none-test
TEST check-qtest-avr: tests/qtest/qmp-test
TEST check-qtest-avr: tests/qtest/qmp-cmd-test
TEST check-qtest-avr: tests/qtest/qom-test
TEST check-qtest-avr: tests/qtest/test-hmp
TEST check-qtest-avr: tests/qtest/qos-test

CI results:
. https://cirrus-ci.com/build/5697049146425344
. https://gitlab.com/philmd/qemu/-/pipelines/165328058
. https://travis-ci.org/github/philmd/qemu/builds/705817933
. https://app.shippable.com/github/philmd/qemu/runs/822/summary/console

# gpg: Signature made Sat 11 Jul 2020 10:03:11 BST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/avr-port-20200711: (32 commits)
target/avr/disas: Fix store instructions display order
target/avr/cpu: Fix $PC displayed address
target/avr/cpu: Drop tlb_flush() in avr_cpu_reset()
target/avr: Add section into QEMU documentation
tests/acceptance: Test the Arduino MEGA2560 board
tests/boot-serial: Test some Arduino boards (AVR based)
hw/avr: Add limited support for some Arduino boards
hw/avr: Add some ATmega microcontrollers
hw/avr: Add support for loading ELF/raw binaries
hw/misc: avr: Add limited support for power reduction device
hw/timer: avr: Add limited support for 16-bit timer peripheral
hw/char: avr: Add limited support for USART peripheral
tests/machine-none: Add AVR support
target/avr: Register AVR support with the rest of QEMU
target/avr: Add support for disassembling via option '-d in_asm'
target/avr: Initialize TCG register variables
target/avr: Add instruction translation - CPU main translation function
target/avr: Add instruction translation - MCU Control Instructions
target/avr: Add instruction translation - Bit and Bit-test Instructions
target/avr: Add instruction translation - Data Transfer Instructions
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

target/avr: CPU class: Add GDB support

This includes GDB hooks for reading from wnd wrtiting to AVR
registers, and xml register definition file as well.

[AM: Split a larger AVR introduction patch i

target/avr: CPU class: Add GDB support

This includes GDB hooks for reading from wnd wrtiting to AVR
registers, and xml register definition file as well.

[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Co-developed-by: Michael Rolnik <mrolnik@gmail.com>
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[thuth: Fixed avr_cpu_gdb_read_register() parameter]
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-7-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

show more ...