Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0 |
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1406b7fc |
| 03-Jul-2024 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio: features,fixes
A bunch of improvements: - vhost dirty log is now only scanned once, not once per de
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio: features,fixes
A bunch of improvements: - vhost dirty log is now only scanned once, not once per device - virtio and vhost now support VIRTIO_F_NOTIFICATION_DATA - cxl gained DCD emulation support - pvpanic gained shutdown support - beginning of patchset for Generic Port Affinity Structure - s3 support - friendlier error messages when boot fails on some illegal configs - for vhost-user, VHOST_USER_SET_LOG_BASE is now only sent once - part of vhost-user support for any POSIX system - not yet enabled due to qtest failures - sr-iov VF setup code has been reworked significantly - new tests, particularly for risc-v ACPI - bugfixes
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (85 commits) hw/pci: Replace -1 with UINT32_MAX for romsize pcie_sriov: Register VFs after migration pcie_sriov: Remove num_vfs from PCIESriovPF pcie_sriov: Release VFs failed to realize pcie_sriov: Reuse SR-IOV VF device instances pcie_sriov: Ensure VF function number does not overflow pcie_sriov: Do not manually unrealize hw/ppc/spapr_pci: Do not reject VFs created after a PF hw/ppc/spapr_pci: Do not create DT for disabled PCI device hw/pci: Rename has_power to enabled virtio-iommu: Clear IOMMUDevice when VFIO device is unplugged virtio: remove virtio_tswap16s() call in vring_packed_event_read() hw/cxl/events: Mark cxl-add-dynamic-capacity and cxl-release-dynamic-capcity unstable hw/cxl/events: Improve QMP interfaces and documentation for add/release dynamic capacity. tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs meson.build: Add RISC-V to the edk2-target list tests/data/acpi/virt: Move ARM64 ACPI tables under aarch64/${machine} path tests/data/acpi: Move x86 ACPI tables under x86/${machine} path tests/qtest/bios-tables-test.c: Set "arch" for x86 tests ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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c5614ee3 |
| 27-May-2024 |
Thomas Weißschuh <thomas@t-8ch.de> |
linux-headers: update to 6.10-rc1
Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Message-Id: <20240527-pvpanic-shutdown-v8-2-5a28ec02558b@t-8ch.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com
linux-headers: update to 6.10-rc1
Signed-off-by: Thomas Weißschuh <thomas@t-8ch.de> Message-Id: <20240527-pvpanic-shutdown-v8-2-5a28ec02558b@t-8ch.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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34eac35f |
| 10-Jan-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging
RISC-V PR for 9.0
* Make vector whole-register move (vmv) depend on vtype register * Fix th.dcache.cval1
Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging
RISC-V PR for 9.0
* Make vector whole-register move (vmv) depend on vtype register * Fix th.dcache.cval1 priviledge check * Don't allow write mstatus_vs without RVV * Use hwaddr instead of target_ulong for RV32 * Fix machine IDs QOM getters\ * Fix KVM reg id sizes * ACPI: Enable AIA, PLIC and update RHCT * Fix the interrupts-extended property format of PLIC * Add support for Zacas extension * Add amocas.[w,d,q] instructions * Document acpi parameter of virt machine * RVA22 profiles support * Remove group setting of KVM AIA if the machine only has 1 socket * Add RVV CSRs to KVM * sifive_u: Update S-mode U-Boot image build instructions * Upgrade OpenSBI from v1.3.1 to v1.4 * pmp: Ignore writes when RW=01 and MML=0 * Assert that the CSR numbers will be correct * Don't adjust vscause for exceptions * Ensure mideleg is set correctly on reset
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmWeW8kACgkQr3yVEwxT # gBMB3BAAtpb7dC/NqDOjo/LjGf81wYUnF0KcfJUIbuHEM9S03mKJEvngV/sUhg+A # fzsoJazijQZk2+Y02WLT/o+ppRDegb4P6n54Nn13xr024Dn2jf45+EKDLI+vtU5y # lhwp/LH3SEo2MM/Qr0njl8+jJ7W9adhZeK6x+NFaLaQJ291xupbcwEnScdv2bPAo # gvbM6yrfUoZ25MsQKIDGssozdGRwOD/keAT0q8C0gKDamqXBDrI80BOVhRms+uLm # R33DXsAegPKluJTa9gfaWFI0eK34WHXRvSIjE36nZlGNNgqLAVdM2/QozMVz4cKA # Ymz1nzqB9HeSn1pM4KCK/Y3LH89qLGWtyHYgldiDXA/wSyKajwkbXSWFOT9gPDqV # i+5BRDvU0zIeMIt+ROqNKgx1Hry6U2aycMNsdHTmygJbGEpiTaXuES5tt+LKsyHe # w/7a6wPd/kh9LQhXYQ4qbn7L534tWvn8zWyvKLZLxmYPcOn6SdjFbKWmk5ARky2W # sx9ojn9ANlYaLfzQ3TMRcIhWD6n8Si3KFNiQ3353E8xkRkyfu0WHyXAy8/kIc5UT # nScO2YD68XkdkcLF6uLUKuGiVZXFWXRY1Ttz9tvEmBckVsg6TIkoMONHeUWNP7ly # A0bJwN5qEOk6XIYKHWwX5UzvkcfUpOb5VmuLuv3gRoNX0A7/+fc= # =5K9J # -----END PGP SIGNATURE----- # gpg: Signature made Wed 10 Jan 2024 08:56:41 GMT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu: (65 commits) target/riscv: Ensure mideleg is set correctly on reset target/riscv: Don't adjust vscause for exceptions target/riscv: Assert that the CSR numbers will be correct target/riscv: pmp: Ignore writes when RW=01 and MML=0 roms/opensbi: Upgrade from v1.3.1 to v1.4 docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions target/riscv/kvm: add RVV and Vector CSR regs target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize() linux-headers: riscv: add ptrace.h linux-headers: Update to Linux v6.7-rc5 target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket target/riscv: add rva22s64 cpu target/riscv: add RVA22S64 profile target/riscv: add 'parent' in profile description target/riscv: add satp_mode profile support target/riscv/cpu.c: add riscv_cpu_is_32bit() target/riscv/cpu.c: finalize satp_mode earlier target/riscv: add priv ver restriction to profiles target/riscv: implement svade target/riscv: add 'rva22u64' CPU ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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efb91426 |
| 18-Dec-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
linux-headers: Update to Linux v6.7-rc5
We'll add a new RISC-V linux-header file, but first let's update all headers.
Headers for 'asm-loongarch' were added in this update.
Signed-off-by: Daniel H
linux-headers: Update to Linux v6.7-rc5
We'll add a new RISC-V linux-header file, but first let's update all headers.
Headers for 'asm-loongarch' were added in this update.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231218204321.75757-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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9a8af699 |
| 13-Sep-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-request-2023-09-12' of https://gitlab.com/thuth/qemu into staging
* Enable AP (crypto adapter) instructions for s390x PV-guests * Allow NVME for s390x machines * Update Linux headers
Merge tag 'pull-request-2023-09-12' of https://gitlab.com/thuth/qemu into staging
* Enable AP (crypto adapter) instructions for s390x PV-guests * Allow NVME for s390x machines * Update Linux headers to v6.6-rc1
# -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmUATY8RHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVjBhAAlfXhQuxFdSRkPLyPgSuAInGTZfsW7A56 # 6vunyzP3ZyY5G0WtbgKZ5ovDIfjzlNYvkxWmQ4m4PWEY2JaBKOqeS9+lFkdZmGD9 # Sj1u+EereQS5MsJ31Vg2LHDKv5QbtNbVOq4KIm30qpzj1OfhfZzzqU0tGnaDlz/T # PW2bSQl4cGHExcYpprWx02cXsMnodWwGV2FTgtc9D42YyE1q5IDX8phjFFzUHfcQ # p3cjM0S2M8KOGJ5+0w2/0C4DEKgLH0OuA/JY3W+f94O+jdqoYUJpom4m6FywIKrr # 38c7UqQESh7r/te1UkgvxfVCbTlptsS21xQNbsa+TS/apP6IMU7VJI3N14Qshtba # cqcP54aGC+9v5FRz7E5njCJWJQv9JWInrKYTEEtSTFCguGCQO2owulba70MNrQc8 # hQkBXOzqnqYVxdktcHkbnq6QZoKLfsGAxfarQPPJySNUyGgoaM0JFlzp3z0hjAHY # aGRZdN4kU+hF7/0RQygYDN4AzTQhn3EMZ6q6o81xVeKzfbziA3fCLXX5J1bd+rO8 # 3LKPrmOuk3dadRVlVTyFrtlG9SEMRen8dh12oru28ebW2WTeYm71zQf7SCPGzaKE # hJMtlN7B9ogGxDpLJvTDLHbKNbwyIcW00GjyWiUwBg88ACg63tulD2kpUxBs2PwF # bVk/lIWMqL0= # =zeRZ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 12 Sep 2023 07:37:51 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2023-09-12' of https://gitlab.com/thuth/qemu: tests/qtest/pflash: Clean up local variable shadowing kconfig: Add NVME to s390x machines target/s390x: AP-passthrough for PV guests target/s390x/kvm: Refactor AP functionalities linux-headers: Update to Linux v6.6-rc1 s390x: do a subsystem reset before the unprotect on reboot s390x/ap: fix missing subsystem reset registration
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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da3c22c7 |
| 12-Sep-2023 |
Thomas Huth <thuth@redhat.com> |
linux-headers: Update to Linux v6.6-rc1
This update contains the required header changes for the "target/s390x: AP-passthrough for PV guests" patch from Steffen Eiden.
Message-ID: <20230912093432.1
linux-headers: Update to Linux v6.6-rc1
This update contains the required header changes for the "target/s390x: AP-passthrough for PV guests" patch from Steffen Eiden.
Message-ID: <20230912093432.180041-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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7c18f2d6 |
| 29-Apr-2023 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* Fix compilation issues under Debian 10 * Update kernel headers to 6.3rc5 * Suppress GCC13 false positive in aio_bh_poll() *
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* Fix compilation issues under Debian 10 * Update kernel headers to 6.3rc5 * Suppress GCC13 false positive in aio_bh_poll() * Add new x86 feature bits * Coverity fixes * More steps towards removing qatomic_mb_set/read * Fix reduced-phys-bits value for AMD SEV
# -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmRNC0IUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNo0wgArWNGKZpbmQ0e5L6ajMvaaPmg4mVL # a2SJGU0TwTp0fUgZr14z2iwzIpSqQrsqhzTIAzOTs0OICDBPBuNvnRucMa+SVQGO # Tc89YAwBVDo66dAKhWi+WR9tx7sTFCso0nbsBfczzdnwAw3g1MJ87Ueqc5tlPGBK # E7YSAD6l4UuogoN5BLU7bSsG/X7bwcyzeUXRB4ik+Z9abWd4DH9qiROnBKLMmBLK # nAi47h8b8MltWORpO+wf6HtkMKi37SAzl9VLHVuHcRhIdY/JhWCRhYSo0HXhgX66 # JLVkyxFpIndT0dUW/xnqATGez92FRZyTxHbxbAcWM0SoC1jOVfUXB+7Gdw== # =vxou # -----END PGP SIGNATURE----- # gpg: Signature made Sat 29 Apr 2023 01:19:14 PM BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: cpus-common: stop using mb_set/mb_read async: Suppress GCC13 false positive in aio_bh_poll() tests: vhost-user-test: release mutex on protocol violation Update linux headers to v6.3rc5 update-linux-headers.sh: Add missing kernel headers. Fix libvhost-user.c compilation. target/i386: Add support for PREFETCHIT0/1 in CPUID enumeration target/i386: Add support for AVX-NE-CONVERT in CPUID enumeration target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration target/i386: Add support for AVX-IFMA in CPUID enumeration target/i386: Add support for AMX-FP16 in CPUID enumeration target/i386: Add support for CMPCCXADD in CPUID enumeration i386/cpu: Update how the EBX register of CPUID 0x8000001F is set i386/sev: Update checks and information related to reduced-phys-bits qemu-options.hx: Update the reduced-phys-bits documentation qapi, i386/sev: Change the reduced-phys-bits value from 5 to 1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v8.0.0 |
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c5c0fdbe |
| 05-Apr-2023 |
David 'Digit' Turner <digit@google.com> |
Update linux headers to v6.3rc5
commit 7e364e56293bb98cae1b55fd835f5991c4e96e7d
Signed-off-by: David 'Digit' Turner <digit@google.com> Message-Id: <20230405172109.3081788-4-digit@google.com> Signed
Update linux headers to v6.3rc5
commit 7e364e56293bb98cae1b55fd835f5991c4e96e7d
Signed-off-by: David 'Digit' Turner <digit@google.com> Message-Id: <20230405172109.3081788-4-digit@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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