Merge tag 'pull-target-arm-20230216' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Some mostly M-profile-related code cleanups
* avocado: Retire the boot_linu
Merge tag 'pull-target-arm-20230216' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Some mostly M-profile-related code cleanups
* avocado: Retire the boot_linux.py AArch64 TCG tests
* hw/arm/smmuv3: Add GBPA register
* arm/virt: don't try to spell out the accelerator
* hw/arm: Attach PSPI module to NPCM7XX SoC
* Some cleanup/refactoring patches aiming towards
allowing building Arm targets without CONFIG_TCG
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmPuY50ZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3oKND/9Cy7/XlMBOq1vlEM/TG7eK
# Jq582mUDsOqnebDZLEYheWe7wDzIHpoAZfCwOL1sLDbzjjglYXgQu7J3fQvuSofo
# QJBKkJiiATHCQb3I+A7VITl0pyW3lcRy9zZ7E5O9WdbbBcKIC8dwTNyiTAEmKyL9
# ldYxfCZiMl+j+za3uNUxnlEd3oC15UZZfGAi++KjdfdFH6TxyGRhkiAI3iP4QD7s
# aHo+9/TEyl1b9ApjXWymlgupwLeAOI3TwCq30lyBttxh9aU/hUkBttdc+oo+ymTH
# EuOB4IM2O7jCjGMKAeg7jlYfgLJRradaOsY4g0K0VxD/wGRTp6Qehmt//mzYwYYb
# izprDDb1UbJAH5OsFFPNevxQjJHfOOFYs+ObvadRgvLFTPuid8+1YNleknPxp7qm
# jRC9/DYekqcxU2mlEwuPApFNhZBoxwnJhFEHfmO8SCqre4+QfDNbGhUxPuHORt6V
# 0xLzaSC1L6RALLsDnhgYK/Iz8vA/2HmrcO+FC0TlIeKcGUV2xOMQB8+DRlsrzpEz
# KzrjXyuLqUOIWN6iGThxOG72qPd94BKO3SHue7r4BCYpDdeHIbQUC67cBq6b1LZ4
# QDOoeHwuTo5GRnAYoc+lQ7HyEfGiWy38wApQihZ3EOndot6DN/AD8nRC2632Hidu
# evQUClDbeXZDTv87AfIojg==
# =M2nc
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 16 Feb 2023 17:10:53 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20230216' of https://git.linaro.org/people/pmaydell/qemu-arm: (30 commits)
tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
tests/qtest: arm-cpu-features: Match tests to required accelerators
target/arm: Use "max" as default cpu for the virt machine with KVM
tests/avocado: Tag TCG tests with accel:tcg
tests/avocado: Skip tests that require a missing accelerator
target/arm: Move cpregs code out of cpu.h
target/arm: Move PC alignment check
target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
target/arm: wrap psci call with tcg_enabled
target/arm: rename handle_semihosting to tcg_handle_semihosting
hw/arm/smmu-common: Fix TTB1 handling
hw/arm/smmu-common: Support 64-bit addresses
hw/arm: Attach PSPI module to NPCM7XX SoC
hw/ssi: Add Nuvoton PSPI Module
MAINTAINERS: Add myself to maintainers and remove Havard
arm/virt: don't try to spell out the accelerator
hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
hw/arm/smmuv3: Add GBPA register
tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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