Merge tag 'pull-request-2024-10-07' of https://gitlab.com/thuth/qemu into staging

* Mark "gluster" support as deprecated
* Update CI to use macOS 14 instead of 13, and add a macOS 15 job
* Use gitla

Merge tag 'pull-request-2024-10-07' of https://gitlab.com/thuth/qemu into staging

* Mark "gluster" support as deprecated
* Update CI to use macOS 14 instead of 13, and add a macOS 15 job
* Use gitlab mirror for advent calendar test images (seems more stable)
* Bump timeouts of some tests
* Remove CRIS disassembler
* Some m68k and s390x cleanups with regards to load and store APIs

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# gpg: Signature made Mon 07 Oct 2024 12:49:02 BST
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2024-10-07' of https://gitlab.com/thuth/qemu:
tests/functional: Bump timeout of some tests
tests/functional: Switch back to the gitlab URLs for the advent calendar tests
target/s390x: Use explicit big-endian LD/ST API
target/s390x: Replace ldtul_p() -> ldq_p()
hw/s390x: Use explicit big-endian LD/ST API
target/m68k: Use explicit big-endian LD/ST API
hw/m68k: Use explicit big-endian LD/ST API
gitlab-ci/build-oss-fuzz: print FAILED marker in case the test failed and run all tests
disas: Remove CRIS disassembler
.gitlab-ci.d/cirrus: Add manual testing of macOS 15 (Sequoia)
.gitlab-ci.d/cirrus: Drop support for macOS 13 (Ventura)
docs: Mark "gluster" support in QEMU as deprecated

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

disas: Remove CRIS disassembler

We just removed the CRIS target, the disassembler is now dead code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240904143603.52934-15-ph

disas: Remove CRIS disassembler

We just removed the CRIS target, the disassembler is now dead code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240904143603.52934-15-philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

Merge tag 'housekeeping-20240424' of https://github.com/philmd/qemu into staging

Removal of deprecated code

- Remove the Nios II target and hardware
- Remove pvrdma device and rdmacm-mux helper
- R

Merge tag 'housekeeping-20240424' of https://github.com/philmd/qemu into staging

Removal of deprecated code

- Remove the Nios II target and hardware
- Remove pvrdma device and rdmacm-mux helper
- Remove GlusterFS RDMA protocol handling
- Update Sriram Yagnaraman mail address

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# gpg: Signature made Wed 24 Apr 2024 07:12:22 AM PDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* tag 'housekeeping-20240424' of https://github.com/philmd/qemu:
block/gluster: Remove deprecated RDMA protocol handling
hw/rdma: Remove deprecated pvrdma device and rdmacm-mux helper
hw/timer: Remove the ALTERA_TIMER model
target/nios2: Remove the deprecated Nios II target
MAINTAINERS: Update Sriram Yagnaraman mail address

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/nios2: Remove the deprecated Nios II target

The Nios II target is deprecated since v8.2 in commit 9997771bc1
("target/nios2: Deprecate the Nios II architecture").

Remove:
- Buildsys / CI inf

target/nios2: Remove the deprecated Nios II target

The Nios II target is deprecated since v8.2 in commit 9997771bc1
("target/nios2: Deprecate the Nios II architecture").

Remove:
- Buildsys / CI infra
- User emulation
- System emulation (10m50-ghrd & nios2-generic-nommu machines)
- Tests

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
Message-Id: <20240327144806.11319-3-philmd@linaro.org>

show more ...

Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging

maintainer updates (tests, gdbstub, plugins):

- expand QOS_PATH_MAX_ELEMENT_SIZE to avoid LTO issues

Merge tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu into staging

maintainer updates (tests, gdbstub, plugins):

- expand QOS_PATH_MAX_ELEMENT_SIZE to avoid LTO issues
- support fork-follow-mode in gdbstub
- new thread-safe scoreboard API for TCG plugins
- suppress showing opcodes in plugin disassembly

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# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44

* tag 'pull-maintainer-updates-060324-1' of https://gitlab.com/stsquad/qemu: (29 commits)
target/riscv: honour show_opcodes when disassembling
target/loongarch: honour show_opcodes when disassembling
disas/hppa: honour show_opcodes
disas: introduce show_opcodes
plugins: cleanup codepath for previous inline operation
plugins: remove non per_vcpu inline operation from API
contrib/plugins/howvec: migrate to new per_vcpu API
contrib/plugins/hotblocks: migrate to new per_vcpu API
tests/plugin/bb: migrate to new per_vcpu API
tests/plugin/insn: migrate to new per_vcpu API
tests/plugin/mem: migrate to new per_vcpu API
tests/plugin: add test plugin for inline operations
plugins: add inline operation per vcpu
plugins: implement inline operation relative to cpu_index
plugins: define qemu_plugin_u64
plugins: scoreboard API
tests/tcg: Add two follow-fork-mode tests
gdbstub: Implement follow-fork-mode child
gdbstub: Introduce gdb_handle_detach_user()
gdbstub: Introduce gdb_handle_set_thread_user()
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

disas: introduce show_opcodes

For plugins we don't expect the raw opcodes in the disassembly. We
already deal with this by hand crafting our capstone call but for
other diassemblers we need a flag.

disas: introduce show_opcodes

For plugins we don't expect the raw opcodes in the disassembly. We
already deal with this by hand crafting our capstone call but for
other diassemblers we need a flag. Introduce show_opcodes which
defaults to off.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240305121005.3528075-27-alex.bennee@linaro.org>

show more ...

Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu into staging

Second RISC-V PR for 8.1

* Skip Vector set tail when vta is zero
* Move zc* out of the experimental prope

Merge tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu into staging

Second RISC-V PR for 8.1

* Skip Vector set tail when vta is zero
* Move zc* out of the experimental properties
* Mask the implicitly enabled extensions in isa_string based on priv version
* Rework CPU extension validation and validate MISA changes
* Fixup PMP TLB cacheing errors
* Writing to pmpaddr and MML/MMWP correctly triggers TLB flushes
* Fixup PMP bypass checks
* Deny access if access is partially inside a PMP entry
* Correct OpenTitanState parent type/size
* Fix QEMU crash when NUMA nodes exceed available CPUs
* Fix pointer mask transformation for vector address
* Updates and improvements for Smstateen
* Support disas for Zcm* extensions
* Support disas for Z*inx extensions
* Remove unused decomp_rv32/64 value for vector instructions
* Enable PC-relative translation
* Assume M-mode FW in pflash0 only when "-bios none"
* Support using pflash via -blockdev option
* Add vector registers to log
* Clean up reference of Vector MTYPE
* Remove the check for extra Vector tail elements
* Smepmp: Return error when access permission not allowed in PMP
* Fixes for smsiaddrcfg and smsiaddrcfgh in AIA

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# gpg: Signature made Wed 14 Jun 2023 03:17:14 AM CEST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20230614' of https://github.com/alistair23/qemu: (60 commits)
hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
target/riscv: Smepmp: Return error when access permission not allowed in PMP
target/riscv/vector_helper.c: Remove the check for extra tail elements
target/riscv/vector_helper.c: clean up reference of MTYPE
target/riscv: Fix initialized value for cur_pmmask
util/log: Add vector registers to log
docs/system: riscv: Add pflash usage details
riscv/virt: Support using pflash via -blockdev option
hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none"
target/riscv: Remove pc_succ_insn from DisasContext
target/riscv: Enable PC-relative translation
target/riscv: Use true diff for gen_pc_plus_diff
target/riscv: Change gen_set_pc_imm to gen_update_pc
target/riscv: Change gen_goto_tb to work on displacements
target/riscv: Introduce cur_insn_len into DisasContext
target/riscv: Fix target address to update badaddr
disas/riscv.c: Remove redundant parentheses
disas/riscv.c: Fix lines with over 80 characters
disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions
disas/riscv.c: Support disas for Z*inx extensions
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

disas: Change type of disassemble_info.target_info to pointer

Use pointer to pass more information of target to disasembler,
such as pass cpu.cfg related information in following commits.

Signed-of

disas: Change type of disassemble_info.target_info to pointer

Use pointer to pass more information of target to disasembler,
such as pass cpu.cfg related information in following commits.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230523093539.203909-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

Merge tag 'pull-request-2023-03-20' of https://gitlab.com/thuth/qemu into staging

* Mark Nios II as orphan
* Many s390x emulation fixes
* Disable flaky complete_in_standby blockjob unit test
* White

Merge tag 'pull-request-2023-03-20' of https://gitlab.com/thuth/qemu into staging

* Mark Nios II as orphan
* Many s390x emulation fixes
* Disable flaky complete_in_standby blockjob unit test
* White space cleanups in various files

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# gpg: Signature made Mon 20 Mar 2023 12:40:42 GMT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2023-03-20' of https://gitlab.com/thuth/qemu: (24 commits)
replace TABs with spaces
qemu/osdep: Switch position of "extern" and "G_NORETURN"
tests/unit/test-blockjob: Disable complete_in_standby test
target/s390x/tcg/mem_helper: Remove bad assert() statement
tests/tcg/s390x: Test unaligned accesses
target/s390x: Update do_unaligned_access() comment
target/s390x: Handle STGRL to non-aligned addresses
target/s390x: Handle STRL to non-aligned addresses
target/s390x: Handle CLRL and CLGFRL with non-aligned addresses
target/s390x: Handle CGRL and CLGRL with non-aligned addresses
target/s390x: Handle CRL and CGFRL with non-aligned addresses
target/s390x: Handle LLGFRL from non-aligned addresses
target/s390x: Handle LRL and LGFRL from non-aligned addresses
target/s390x: Handle LGRL from non-aligned addresses
target/s390x: Handle EXECUTE of odd addresses
target/s390x: Handle branching to odd addresses
tests/tcg/s390x: Add ex-relative-long.c
target/s390x: Fix EXECUTE of relative long instructions
tests/tcg/s390x: Add rxsbg.c
target/s390x: Fix R[NOX]SBG with T=1
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

replace TABs with spaces

Bring the files in line with the QEMU coding style, with spaces
for indentation.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/378
Signed-off-by: Yeqi Fu <fufuyqq

replace TABs with spaces

Bring the files in line with the QEMU coding style, with spaces
for indentation.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/378
Signed-off-by: Yeqi Fu <fufuyqqqqqq@gmail.com>
Message-Id: <20230315032649.57568-1-fufuyqqqqqq@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

* block/iscsi: fix double-free on BUSY or similar statuses
* catch [accel] entry without accelerator
* target/i386: various f

Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

* block/iscsi: fix double-free on BUSY or similar statuses
* catch [accel] entry without accelerator
* target/i386: various fixes for BMI and ADX instructions
* make the contents of meson-buildoptions.sh stable

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# gpg: Signature made Sun 12 Feb 2023 16:00:55 GMT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83

* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
libqtest: ensure waitpid() is only called once
libqtest: split qtest_spawn_qemu function
target/i386: fix ADOX followed by ADCX
target/i386: Fix C flag for BLSI, BLSMSK, BLSR
target/i386: Fix BEXTR instruction
tests/tcg/i386: Introduce and use reg_t consistently
vl: catch [accel] entry without accelerator
block/iscsi: fix double-free on BUSY or similar statuses
remove unnecessary extern "C" blocks
build: make meson-buildoptions.sh stable

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

remove unnecessary extern "C" blocks

A handful of header files in QEMU are wrapped with extern "C" blocks.
These are not necessary: there are C++ source files anymore in QEMU,
and even where there w

remove unnecessary extern "C" blocks

A handful of header files in QEMU are wrapped with extern "C" blocks.
These are not necessary: there are C++ source files anymore in QEMU,
and even where there were some, they did not include most of these
files anyway.

Remove them for consistency.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

Merge tag 'pull-la-20220606' of https://gitlab.com/rth7680/qemu into staging

Initial LoongArch support.

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmKeiRYdHHJpY

Merge tag 'pull-la-20220606' of https://gitlab.com/rth7680/qemu into staging

Initial LoongArch support.

# -----BEGIN PGP SIGNATURE-----
#
# iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmKeiRYdHHJpY2hhcmQu
# aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV85Kgf/buBy5+0y51NKOpTI
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# +YKN4jobvJiLVhD1wDVJqp/2r9gcnX11EWZk+ZC+pIiEqYZpWRcQdEGVh4Ymhig8
# 0LK/8HRSyw0AecX/01hcGWvYCC0ldFicwN69AD42BqM+7WD+3jnV8FJL8qqq766G
# xuCNHz0eDcVgfw9bCEyhFmhgiBFvOXNCtyDOV0qVn7eee9nIrFZcsGyBqeI/T1el
# e7uz8Q==
# =l8TD
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 06 Jun 2022 04:09:10 PM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-la-20220606' of https://gitlab.com/rth7680/qemu: (43 commits)
target/loongarch: 'make check-tcg' support
tests/tcg/loongarch64: Add hello/memory test in loongarch64 system
target/loongarch: Add gdb support.
hw/loongarch: Add LoongArch virt power manager support.
hw/loongarch: Add LoongArch load elf function.
hw/loongarch: Add LoongArch ls7a rtc device support
hw/loongarch: Add some devices support for 3A5000.
Enable common virtio pci support for LoongArch
hw/loongarch: Add irq hierarchy for the system
hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
hw/loongarch: Add LoongArch ipi interrupt support(IPI)
hw/loongarch: Add support loongson3 virt machine type.
target/loongarch: Add timer related instructions support.
target/loongarch: Add other core instructions support
target/loongarch: Add TLB instruction support
target/loongarch: Add LoongArch IOCSR instruction
target/loongarch: Add LoongArch CSR instruction
target/loongarch: Add constant timer support
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/loongarch: Add disassembler

This patch adds support for disassembling via option '-d in_asm'.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongso

target/loongarch: Add disassembler

This patch adds support for disassembling via option '-d in_asm'.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-17-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

Merge tag 'pull-request-2022-05-09' of https://gitlab.com/thuth/qemu into staging

* Remove redundant/obsolete x86, arm and ppc disassemblers (Capstone is better)
* Limit some Xen-related code to bui

Merge tag 'pull-request-2022-05-09' of https://gitlab.com/thuth/qemu into staging

* Remove redundant/obsolete x86, arm and ppc disassemblers (Capstone is better)
* Limit some Xen-related code to builds where Xen is really available
* Remove hxtool-conv.pl and remove STEXI/ETEXI references from the docs
* Update MinGW and OpenBSD to a more recent version in the CI
* Warn user if the -vga flag is passed but no vga device is created

# -----BEGIN PGP SIGNATURE-----
#
# iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmJ4s8wRHHRodXRoQHJl
# ZGhhdC5jb20ACgkQLtnXdP5wLbVszRAAjIJVvJgWJUlRqap/SFV3tX89jIhDKi3+
# luTBhjsDsNoFLd6ARwpykyM9dFF5sEqAHr7tjWtL7nuJIEjsnhwcUi/WUhzfkp44
# mEjmFaZL9WqXE3CD5Hd3HGhXpt5830Nmza59UvLEslLzNrmrEqQVR8cPVmmNCkG9
# diS+tata2NI1p5CF2ScxpxCfxNbDrhrhWN9cU76BM6hut1KH1oA4+fdn2QrSr610
# Y6YWvw+NlzXt9yCW2qDSUlLJvKT4VQ8r4bZ6ab/SiYzw0aHSFK14+150oyPYl91t
# dN7LAyDrheZQ/R46lb76fI57kTmXRQLK0WtxK9dRJTF0hgpGgAEbMNdOOz07oQ45
# oBTFbIa7+mydgmfMZ1uZGSpUI55OOb0VE/N974MJOgXCjlFGLn0YaZezBErViBLd
# ugILNle3IbZWDOwQv4n1fT3VB+2s+I1E3/qPzeDSbGAIkWm41g/4MHpkc5JGMb0j
# dquDo98YdEW/gpFUSFk2u859MA/jMlla77KsOcHpBhKOvLnQtxse+Bi5If4NiR+K
# NPBObMLd2j5rFtUUfDQ1fXEeAkZiITbHNR4yOiOu1tuyTm214xqMuc0/JpqWf+cr
# +fd/i17j2M9Btn7EZePemuyAOqLec41QfOGid320yHS75nhBCdVkDA+g7J0MlOVF
# tFBkhBJ0F+U=
# =8A+p
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 08 May 2022 11:25:16 PM PDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [undefined]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2022-05-09' of https://gitlab.com/thuth/qemu:
docs/devel/writing-monitor-commands: Replace obsolete STEXI/ETEXI tags
Warn user if the vga flag is passed but no vga device is created
tests/vm: update openbsd to release 7.1
gitlab-ci: Upgrade mingw base package.
cirrus/win32: upgrade mingw base packages
doc: remove hxtool-conv.pl
qemu-options: Limit the -xen options to x86 and arm
softmmu/vl: Fence 'xenfb' if Xen support is not compiled in
disas: Remove old libopcode ppc disassembler
disas: Remove old libopcode i386 disassembler
disas: Remove old libopcode arm disassembler

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

disas: Remove old libopcode ppc disassembler

Capstone should be superior to the old libopcode disassembler,
so we can drop the old file nowadays.

Message-Id: <20220505173619.488350-1-thuth@redhat.c

disas: Remove old libopcode ppc disassembler

Capstone should be superior to the old libopcode disassembler,
so we can drop the old file nowadays.

Message-Id: <20220505173619.488350-1-thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

disas: Remove old libopcode i386 disassembler

Capstone should be superior to the old libopcode disassembler,
so we can drop the old file nowadays.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Revi

disas: Remove old libopcode i386 disassembler

Capstone should be superior to the old libopcode disassembler,
so we can drop the old file nowadays.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220412165836.355850-4-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

disas: Remove old libopcode arm disassembler

Capstone should be superior to the old libopcode disassembler, so
we can drop the old file nowadays.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Revie

disas: Remove old libopcode arm disassembler

Capstone should be superior to the old libopcode disassembler, so
we can drop the old file nowadays.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220412165836.355850-3-thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

Merge tag 'pull-request-2022-05-04' of https://gitlab.com/thuth/qemu into staging

* Silence the warning about the msa5 feature when using the "max" CPU on s390x
* Implement the s390x Vector-Enhancem

Merge tag 'pull-request-2022-05-04' of https://gitlab.com/thuth/qemu into staging

* Silence the warning about the msa5 feature when using the "max" CPU on s390x
* Implement the s390x Vector-Enhancements Facility 2
* Remove the old libopcode-based s390 disassembler
* Fix branch-relative-long test compilation with Clang

# -----BEGIN PGP SIGNATURE-----
#
# iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmJyXKURHHRodXRoQHJl
# ZGhhdC5jb20ACgkQLtnXdP5wLbX1bg//bSZhEFekeak8nsM2piEwA/d3hEz5aTqN
# 9UW296E3MpE6cyfai+rQw1HzACA/sbOHLGBpOfo+dPkCq7JPhif62xOWd/6pfjvl
# d6+GRB7YusSnyePwQ7AJwWK7xOFi9LqYiqfM7wqUQf/TbetB4/ufssVc47LBsrqR
# 5OWJMRf0G/GItpCCy4IDp1oEJnKI9lGN+VG9hWJePeGYPLelmx0uHH02kgDCOb93
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# ZPmXWTUuewWSnGsJsRK9R8+UQ+nB6x8gxqK1s0dHf2rTgtIgWsx5s9WEdxGqeQ5h
# 5IvIBOML4aXnp2i0QGoGdq4zaDl1ac8AGpLd2jqc9svlHl44Q7NfY2MiWMVGCOP+
# O7DdO/tfmuJyPZS4QolGHghJFycC3Qr3Z42/dJrNK8bwaVGG/ysWkrutxcUzS3z9
# /xkkBWz8Vlktcy4Ft8lqkvofQGUYuJIfbU++EBu6yAp+mSzbO7elE8TZbgpGOVQv
# BFgwW3J4iqI=
# =7QOT
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 04 May 2022 03:59:49 AM PDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [undefined]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2022-05-04' of https://gitlab.com/thuth/qemu:
tests/tcg/s390x: Use a different PCRel32 notation in branch-relative-long.c
disas: Remove old libopcode s390 disassembler
tests/tcg/s390x: Tests for Vector Enhancements Facility 2
target/s390x: add S390_FEAT_VECTOR_ENH2 to qemu CPU model
target/s390x: vxeh2: vector {load, store} byte reversed element
target/s390x: vxeh2: vector {load, store} byte reversed elements
target/s390x: vxeh2: vector {load, store} elements reversed
target/s390x: vxeh2: vector shift double by bit
target/s390x: vxeh2: Update for changes to vector shifts
target/s390x: vxeh2: vector string search
target/s390x: vxeh2: vector convert short/32b
tcg: Implement tcg_gen_{h,w}swap_{i32,i64}
s390x/cpu_models: make "max" match the unmodified "qemu" CPU model under TCG
s390x/cpu_models: drop "msa5" from the TCG "max" model
target/s390x: Fix writeback to v1 in helper_vstl

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

disas: Remove old libopcode s390 disassembler

Capstone should be superior to the old libopcode disassembler,
so we can drop the old file nowadays.

Message-Id: <20220412165836.355850-2-thuth@redhat.

disas: Remove old libopcode s390 disassembler

Capstone should be superior to the old libopcode disassembler,
so we can drop the old file nowadays.

Message-Id: <20220412165836.355850-2-thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>

show more ...

Merge tag 'fixes-pull-request' of gitlab.com:marcandre.lureau/qemu into staging

Fixes and cleanups for 7.0

Hi,

A collection of fixes & cleanup patches that should be safe for 7.0 inclusion.

# gpg

Merge tag 'fixes-pull-request' of gitlab.com:marcandre.lureau/qemu into staging

Fixes and cleanups for 7.0

Hi,

A collection of fixes & cleanup patches that should be safe for 7.0 inclusion.

# gpg: Signature made Tue 22 Mar 2022 12:11:30 GMT
# gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5
# gpg: issuer "marcandre.lureau@redhat.com"
# gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [full]
# gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [full]
# Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5

* tag 'fixes-pull-request' of gitlab.com:marcandre.lureau/qemu: (21 commits)
qapi: remove needless include
Remove trailing ; after G_DEFINE_AUTO macro
tests: remove needless include
error: use GLib to remember the program name
qga: remove bswap.h include
qapi: remove needless include
meson: fix CONFIG_ATOMIC128 check
meson: move int128 checks from configure
qapi: remove needless include
util: remove the net/net.h dependency
util: remove needless includes
scripts/modinfo-collect: remove unused/dead code
Move HOST_LONG_BITS to compiler.h
Simplify HOST_LONG_BITS
compiler.h: replace QEMU_SENTINEL with G_GNUC_NULL_TERMINATED
compiler.h: replace QEMU_WARN_UNUSED_RESULT with G_GNUC_WARN_UNUSED_RESULT
Replace GCC_FMT_ATTR with G_GNUC_PRINTF
Drop qemu_foo() socket API wrapper
m68k/nios2-semi: fix gettimeofday() result check
vl: typo fix in a comment
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Replace GCC_FMT_ATTR with G_GNUC_PRINTF

One less qemu-specific macro. It also helps to make some headers/units
only depend on glib, and thus moved in standalone projects eventually.

Signed-off-by:

Replace GCC_FMT_ATTR with G_GNUC_PRINTF

One less qemu-specific macro. It also helps to make some headers/units
only depend on glib, and thus moved in standalone projects eventually.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard W.M. Jones <rjones@redhat.com>

show more ...

Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging

Second RISC-V PR for QEMU 7.0

- Fix illegal instruction when PMP is disabled
- SiFive PDMA 64-bit support
- Si

Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into staging

Second RISC-V PR for QEMU 7.0

- Fix illegal instruction when PMP is disabled
- SiFive PDMA 64-bit support
- SiFive PLIC cleanups
- Mark Hypervisor extension as non experimental
- Enable Hypervisor extension by default
- Support 32 cores on the virt machine
- Corrections for the Vector extension
- Experimental support for 128-bit CPUs
- stval and mtval support for illegal instructions

# gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054

* tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits)
target/riscv: Implement the stval/mtval illegal instruction
target/riscv: Fixup setting GVA
target/riscv: Set the opcode in DisasContext
target/riscv: actual functions to realize crs 128-bit insns
target/riscv: modification of the trans_csrxx for 128-bit support
target/riscv: helper functions to wrap calls to 128-bit csr insns
target/riscv: adding high part of some csrs
target/riscv: support for 128-bit M extension
target/riscv: support for 128-bit arithmetic instructions
target/riscv: support for 128-bit shift instructions
target/riscv: support for 128-bit U-type instructions
target/riscv: support for 128-bit bitwise instructions
target/riscv: accessors to registers upper part and 128-bit load/store
target/riscv: moving some insns close to similar insns
target/riscv: setup everything for rv64 to support rv128 execution
target/riscv: array for the 64 upper bits of 128-bit registers
target/riscv: separation of bitwise logic and arithmetic helpers
target/riscv: additional macros to check instruction support
qemu/int128: addition of div/rem 128-bit operations
exec/memop: Adding signed quad and octo defines
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

target/riscv: setup everything for rv64 to support rv128 execution

This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
exe

target/riscv: setup everything for rv64 to support rv128 execution

This patch adds the support of the '-cpu rv128' option to
qemu-system-riscv64 so that we can indicate that we want to run rv128
executables.
Still, there is no support for 128-bit insns at that stage so qemu fails
miserably (as expected) if launched with this option.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr
[ Changed by AF
- Rename CPU to "x-rv128"
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

show more ...

Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull-request' into staging

Trivial patches pull request 20211023

# gpg: Signature made Sat 23 Oct 2021 11:30:42 AM PDT
# gpg

Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull-request' into staging

Trivial patches pull request 20211023

# gpg: Signature made Sat 23 Oct 2021 11:30:42 AM PDT
# gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]

* remotes/vivier/tags/trivial-branch-for-6.2-pull-request:
analyze-migration.py: fix extract contents ('-x') errors
analyze-migration.py: fix a long standing typo
README: Fix some documentation URLs
hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device
hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device
hw/nvram: Fix Memory Leak in Xilinx eFuse QOM
softmmu/physmem.c: Fix typo in comment
MAINTAINERS: Add myself as reviewer of 'Machine core' API
disas/nios2: Simplify endianess conversion
disas/nios2: Fix style in print_insn_nios2()
po: update turkish translation

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...