Revision tags: v9.2.0, v9.1.2, v9.1.1 |
|
#
f774a677 |
| 15-Oct-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-target-arm-20241015-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * hw/arm/omap1: Remove unused omap_uwire_attach() method * stm32f405: Add R
Merge tag 'pull-target-arm-20241015-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * hw/arm/omap1: Remove unused omap_uwire_attach() method * stm32f405: Add RCC device to stm32f405 SoC * arm/gicv3: add missing casts * hw/misc: Create STM32L4x5 SYSCFG clock * hw/arm: Add SPI to Allwinner A10 * hw/intc/omap_intc: Remove now-unnecessary abstract base class * hw/char/pl011: Use correct masks for IBRD and FBRD * docs/devel: Convert txt files to rST * Remove MAX111X, MAX7310, DSCM-1XXXX, pcmcia devices (used only by now-removed omap/pxa2xx boards) * vl.c: Remove pxa2xx-specific -portrait and -rotate options * dma: Fix function names in documentation * hw/arm/xilinx_zynq: Add various missing unimplemented devices
# -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmcOeWEZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3jCMD/482mpT1s+mrEJFWSJJXU4G # 8kr4Zj6+NafbayJ0vHTkpSbkEbPxuvDiUqmlnbI+3o11i+Z3IyiaGZbba7dyNnKl # 02MdQavL0dB+eMrcFNofRRvwvsposuj2ixgwTQe6L32HSFdHerVVwuhHM/wfwyCh # DKt7gPRovD/7CtwDOSpyW7cK64WK1IUlE8VEsbFdQbCPkopm55LQ2sLT4TshadpG # A6xcxyLN0x/lHgCmvijB1T09LSc1nQpUEQNIokC4f1Rmy6HNgGDYY1G7GAJf99mT # nWhATuuhZThiYfRbN5KQoS9tGEUduxtkGhHiOgpdXpgc3cS7RusCHoqAnibpsVh3 # TgAkaRAX1d/jQ2KYR2h2jI3nh66ObhrFRT3dkzRZrIvmK9zeWUKmS9lzZ94aVfPH # +MtBPwsO5OhzEABs8WpMY9V1nYaYDsFATMc1akUSaSLn1Er9Uz66NIk+J4Lob4P0 # 78IPvTmwvAIITiqQvkISsc37n5a2/toeaffU2hPKtQLlhyilWynEZA5YItrXSTuk # gYIBxyZSbzGj/ofZ9T9C0GDLbhJp9ksNIpIqRUiHOH3z9b85r7HVZORp+COw/ZXR # UGak6rpJ+XVOxVL/cPRTvZB0RbUHIZh7WLNH2G7Tfv4E4llqL81iuImHXVh/2CXO # 9GWr9qbDLDYQ+BI7ipLAYg== # =n2CA # -----END PGP SIGNATURE----- # gpg: Signature made Tue 15 Oct 2024 15:17:05 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20241015-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (28 commits) hw/arm/xilinx_zynq: Add various missing unimplemented devices dma: Fix function names in documentation vl.c: Remove pxa2xx-specific -portrait and -rotate options hw/block: Remove ecc hw: Remove PCMCIA subsystem hw/ide: Remove DSCM-1XXXX microdrive device model hw/gpio: Remove MAX7310 device hw/adc: Remove MAX111X device docs/devel/lockcnt: Include kernel-doc API documentation include: Move QemuLockCnt APIs to their own header docs/devel/rcu: Convert to rST format docs/devel/multiple-iothreads: Convert to rST format docs/devel/lockcnt: Convert to rST format docs/devel/blkverify: Convert to rST format docs/devel/blkdebug: Convert to rST format hw/char/pl011: Use correct masks for IBRD and FBRD hw/intc/omap_intc: Remove now-unnecessary abstract base class hw/arm: Add SPI to Allwinner A10 hw/ssi: Allwinner A10 SPI emulation tests/qtest: Check STM32L4x5 clock connections ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
8d3dfb62 |
| 14-Oct-2024 |
Strahinja Jankovic <strahinjapjankovic@gmail.com> |
hw/ssi: Allwinner A10 SPI emulation
This patch implements Allwinner A10 SPI controller emulation. Only master-mode functionality is implemented.
Since U-Boot and Linux SPI drivers for Allwinner A10
hw/ssi: Allwinner A10 SPI emulation
This patch implements Allwinner A10 SPI controller emulation. Only master-mode functionality is implemented.
Since U-Boot and Linux SPI drivers for Allwinner A10 perform only byte-wide CPU access (no DMA) to the transmit and receive registers of the peripheral, the emulated controller does not implement DMA control, and supports only byte-wide access to transmit and receive registers (half-word and word accesses will be treated as byte accesses).
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Message-id: 20241001221349.8319-2-strahinja.p.jankovic@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: v9.1.0 |
|
#
93b799fa |
| 26-Jul-2024 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-ppc-for-9.1-2-20240726-1' of https://gitlab.com/npiggin/qemu into staging
fixes
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmai5TsACgkQZ7MCdqhi
Merge tag 'pull-ppc-for-9.1-2-20240726-1' of https://gitlab.com/npiggin/qemu into staging
fixes
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmai5TsACgkQZ7MCdqhi # HK4rgA//eh0ax3JnBGma1rVEDL5n5cdEYV+ATFYGc529CUZFUar3IMqSw3in8bJy # uvQ6Cr/7IuusNEtoiYtdN1yNasqsm3fZB/hZ/Ekz32TsbpBRdkJW3ucavAu2rGM/ # EKRo7Y8gciy/Mj9y2JlIZqsDqYe+gribfGQvIg27DX+caAW/lKQdAdt4oJMTSdmr # XR8JjtMdhUazKrI+bc/4EG6tIQyUdp+S1/z1q6Wthqt58dNRElTjkD9op4AsUWMu # CE4a8ALCZoj3P3m+xf7xi7fT2JC2xgmNRCi3KbbhVEHdbFB6ViNYNuEYRS6GmpdC # C6J/ZR6QXs6KB1KO7EyB+vsuxLX4Eb8aeCFxwMlzJ9Fo4g8JudABXOFzYTKX1xBn # DUIGX91YACV43M2MvP/KuEU4zWpREO+U8MbQs/6s6fYsnCO2eKVJt/0Aaf1hmk37 # gY5Ak2DRx5TBvxlFy87zgHxHWTh/dGZodpN3IvCIDzVLnHGFlfluJbFRaoZSOecb # 1vxDHORjIruLcAxNVEGkJ/6MxOrnjjoUzSPUQcbgJ5BpFZOdeGLiMAULu/HBLBd9 # 7dvVw+PeNEPJttYumljOD6nYc/jENhLQsvkc3++bwGNc/rpi4YngtB4jhT1HV2Cl # oLool2ooKZgV4qx6IzeYo9feElvWVNK5XPzqDpSDlt9MaI+yTYM= # =FxPm # -----END PGP SIGNATURE----- # gpg: Signature made Fri 26 Jul 2024 09:52:27 AM AEST # gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE # gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE
* tag 'pull-ppc-for-9.1-2-20240726-1' of https://gitlab.com/npiggin/qemu: (96 commits) target/ppc: Remove includes from mmu-book3s-v3.h target/ppc/mmu-radix64: Remove externally unused parts from header target/ppc: Unexport some functions from mmu-book3s-v3.h target/ppc/mmu-hash32.c: Move get_pteg_offset32() to the header target/ppc/mmu-hash32.c: Inline and remove ppc_hash32_pte_raddr() target/ppc/mmu_common.c: Remove mmu_ctx_t target/ppc/mmu_common.c: Stop using ctx in get_bat_6xx_tlb() target/ppc: Remove bat_size_prot() target/ppc/mmu_common.c: Use defines instead of numeric constants target/ppc/mmu_common.c: Rename function parameter target/ppc/mmu_common.c: Stop using ctx in ppc6xx_tlb_check() target/ppc/mmu_common.c: Remove key field from mmu_ctx_t target/ppc/mmu_common.c: Init variable in function that relies on it target/ppc/mmu-hash32.c: Inline and remove ppc_hash32_pte_prot() target/ppc: Add function to get protection key for hash32 MMU target/ppc/mmu_common.c: Remove ptem field from mmu_ctx_t target/ppc/mmu_common.c: Inline and remove ppc6xx_tlb_pte_check() target/ppc/mmu_common.c: Simplify a switch statement target/ppc/mmu_common.c: Remove single use local variable target/ppc/mmu_common.c: Convert local variable to bool ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
|
#
29318db1 |
| 26-Jun-2024 |
Chalapathi V <chalapathi.v@linux.ibm.com> |
hw/ssi: Add SPI model
SPI controller device model supports a connection to a single SPI responder. This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function con
hw/ssi: Add SPI model
SPI controller device model supports a connection to a single SPI responder. This provide access to SPI seeproms, TPM, flash device and an ADC controller.
All SPI function control is mapped into the SPI register space to enable full control by firmware. In this commit SPI configuration component is modelled which contains all SPI configuration and status registers as well as the hold registers for data to be sent or having been received.
An existing QEMU SSI framework is used and SSI_BUS is created.
Signed-off-by: Chalapathi V <chalapathi.v@linux.ibm.com> Reviewed-by: Caleb Schlossin <calebs@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Glenn Miles <milesg@linux.ibm.com> [np: Fix FDT macro compile for qtest] Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
show more ...
|
#
4f2fdb10 |
| 02-Feb-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target/arm: fix exception syndrome for AArch32 bkpt insn pci, vmbus, adb, s390x/css-bridge: Switc
Merge tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target/arm: fix exception syndrome for AArch32 bkpt insn pci, vmbus, adb, s390x/css-bridge: Switch buses to 3-phase reset system/vl.c: Fix handling of '-serial none -serial something' target/arm: Add ID_AA64ZFR0_EL1.B16B16 to the exposed-to-userspace set tests/qtest/xlnx-versal-trng-test.c: Drop use of variable length array target/arm: Reinstate "vfp" property on AArch32 CPUs doc/sphinx/hxtool.py: add optional label argument to SRST directive hw/arm: Check for CPU types in machine_run_board_init() for various boards pci-host: designware: Limit value range of iATU viewport register hw/arm: Convert some DPRINTF macros to trace events and guest errors hw/arm: NPCM7XX SoC: Add GMAC ethernet controller devices hw/arm: Implement BCM2835 SPI Controller
# -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmW9C84ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3qS6D/wM0/JGEYfaadpuMEOAx4PG # AnfScbPqVhx9J31P2Ks3VrB5F108aq/SaL2BmCb3BLF/ECChlhBXIjd7ukdHstts # F1TvqtvLGDZQz6wSVUeB0YOvAjGa3vIskn+Xvk9e6Ne6PcXgVnxAof/cPsXUiYNy # 6DJjNiLJ/a9Xgq9rjFO6vzW3AL95U6/FmD2F0pOotWXERhNhoyYVV6RtyeqKlDQP # yFVk5h601YURk9PeNZn9zpOpZqjAM7PxyF3X50N3Sv+G0uoKSr6b+c3/fDJbJo3+ # 0LXomEa8hdheQxm1dLY5OD0JX3bvYxwH41bDg9B0iEdjxUdXt6LfXI9Nvw9BAwix # 8AcGJJUaL4XU4uPfHBpRJApM15+MRb0hqfv4ZcGk8e67IIqVeDbKL2clTQGoHSg1 # KaB0POhtFx//M/uBOyk/FR2gb2eBNU8GuoCgxdDwh0K5ylcaK1YPiX4Tcglu4iS0 # Frvazphb2pO1BK6JiJwN2/9ezzDkDJqTKoSqdc4g3ETVOGnxr+tXwcds3t2iK3g2 # y+pgijDOAT3bJO5kYeGvhoEJPKqXwJ3UQ8zTJsU2XSYwBjIyv5V3oOn6elwYJaWq # yUDTC3QEK61KfnQnfTyLfdGWX1aVzHnYLWmQdO+3cczuQU0s0MP246Z1GAgDtgvD # jGjDBz6mryWvP2H0xSmERQ== # =azdP # -----END PGP SIGNATURE----- # gpg: Signature made Fri 02 Feb 2024 15:35:42 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240202' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) hw/arm: Connect SPI Controller to BCM2835 hw/ssi: Implement BCM2835 SPI Controller tests/qtest: Adding PCS Module test to GMAC Qtest hw/net: GMAC Tx Implementation hw/net: GMAC Rx Implementation tests/qtest: Creating qtest for GMAC Module hw/arm: Add GMAC devices to NPCM7XX SoC hw/net: Add NPCMXXX GMAC device hw/xen: convert stderr prints to error/warn reports hw/xen/xen-hvm-common.c: convert DPRINTF to tracepoints hw/xen/xen-mapcache.c: convert DPRINTF to tracepoints hw/arm/xen_arm.c: convert DPRINTF to trace events and error/warn reports hw/arm/z2: convert DPRINTF to trace events and guest errors hw/arm/strongarm.c: convert DPRINTF to trace events and guest errors pci-host: designware: Limit value range of iATU viewport register hw/arm/zynq: Check for CPU types in machine_run_board_init() hw/arm/vexpress: Check for CPU types in machine_run_board_init() hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
28004fb7 |
| 29-Jan-2024 |
Rayhan Faizel <rayhan.faizel@gmail.com> |
hw/ssi: Implement BCM2835 SPI Controller
This patch adds the SPI controller for the BCM2835. Polling and interrupt modes of transfer are supported. DMA and LoSSI modes are currently unimplemented.
hw/ssi: Implement BCM2835 SPI Controller
This patch adds the SPI controller for the BCM2835. Polling and interrupt modes of transfer are supported. DMA and LoSSI modes are currently unimplemented.
Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Message-id: 20240129221807.2983148-2-rayhan.faizel@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: v8.0.0, v7.2.0, v7.0.0, v6.2.0, v6.1.0 |
|
#
9a7beaad |
| 05-Mar-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging
RISC-V PR for 6.0
This PR is a collection of RISC-V patches: - Improvements to SiFive U OTP - Upgrad
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging
RISC-V PR for 6.0
This PR is a collection of RISC-V patches: - Improvements to SiFive U OTP - Upgrade OpenSBI to v0.9 - Support the QMP dump-guest-memory - Add support for the SiFive SPI controller (sifive_u) - Initial RISC-V system documentation - A fix for the Goldfish RTC - MAINTAINERS updates - Support for high PCIe memory in the virt machine
# gpg: Signature made Thu 04 Mar 2021 14:44:31 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20210304: hw/riscv: virt: Map high mmio for PCIe hw/riscv: virt: Limit RAM size in a 32-bit system hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() hw/riscv: Drop 'struct MemmapEntry' MAINTAINERS: Add a SiFive machine section goldfish_rtc: re-arm the alarm after migration docs/system: riscv: Add documentation for sifive_u machine docs/system: Add RISC-V documentation docs/system: Sort targets in alphabetical order hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card hw/riscv: sifive_u: Add QSPI0 controller and connect a flash hw/ssi: Add SiFive SPI controller support hw/block: m25p80: Add various ISSI flash information hw/block: m25p80: Add ISSI SPI flash support target-riscv: support QMP dump-guest-memory roms/opensbi: Upgrade from v0.8 to v0.9 hw/misc: sifive_u_otp: Use error_report() when block operation fails target/riscv: Declare csr_ops[] with a known size
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
0694dabe |
| 26-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/ssi: Add SiFive SPI controller support
This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported.
Signed-off-by: Bin Meng <bin.meng@wind
hw/ssi: Add SiFive SPI controller support
This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
Revision tags: v5.2.0, v5.0.0, v4.2.0, v4.0.0, v4.0.0-rc1, v4.0.0-rc0 |
|
#
e56d931a |
| 08-Mar-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-kconfig' into staging
Initial Kconfig work, excluding ARM and MIPS
# gpg: Signature made Thu 07 Mar 2019 20:54:27 GMT # gpg:
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-kconfig' into staging
Initial Kconfig work, excluding ARM and MIPS
# gpg: Signature made Thu 07 Mar 2019 20:54:27 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini/tags/for-upstream-kconfig: (54 commits) kconfig: add documentation .travis.yml: test that no-default-device builds do not regress xtensa-softmmu.mak: express dependencies with Kconfig unicore32-softmmu.mak: express dependencies with Kconfig sparc64-softmmu.mak: express dependencies with Kconfig sparc-softmmu.mak: express dependencies with Kconfig sh4-softmmu.mak: express dependencies with Kconfig s390x: express dependencies with Kconfig riscv-softmmu.mak: replace CONFIG_* with Kconfig "select" directives or1k-softmmu.mak: express dependencies with Kconfig nios2-softmmu.mak: express dependencies with Kconfig moxie-softmmu.mak: express dependencies with Kconfig microblaze-softmmu.mak: express dependencies with Kconfig m68k-softmmu.mak: express dependencies with Kconfig lm32-softmmu.mak: express dependencies with Kconfig hppa-softmmu.mak: express dependencies with Kconfig cris-softmmu.mak: express dependencies with Kconfig alpha-softmmu.mak: express dependencies with Kconfig ppc: Express dependencies of the embedded machines with kconfig ppc: Express dependencies of the Sam460EX machines with kconfig ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
1001800c |
| 29-Jan-2019 |
Paolo Bonzini <pbonzini@redhat.com> |
ssi: express dependencies with kconfig
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
#
82f51817 |
| 23-Jan-2019 |
Paolo Bonzini <pbonzini@redhat.com> |
kconfig: introduce kconfig files
The Kconfig files were generated mostly with this script:
for i in `grep -ho CONFIG_[A-Z0-9_]* default-configs/* | sort -u`; do set fnord `git grep -lw $i --
kconfig: introduce kconfig files
The Kconfig files were generated mostly with this script:
for i in `grep -ho CONFIG_[A-Z0-9_]* default-configs/* | sort -u`; do set fnord `git grep -lw $i -- 'hw/*/Makefile.objs' ` shift if test $# = 1; then cat >> $(dirname $1)/Kconfig << EOF config ${i#CONFIG_} bool
EOF git add $(dirname $1)/Kconfig else echo $i $* fi done sed -i '$d' hw/*/Kconfig for i in hw/*; do if test -d $i && ! test -f $i/Kconfig; then touch $i/Kconfig git add $i/Kconfig fi done
Whenever a symbol is referenced from multiple subdirectories, the script prints the list of directories that reference the symbol. These symbols have to be added manually to the Kconfig files.
Kconfig.host and hw/Kconfig were created manually.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20190123065618.3520-27-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
show more ...
|