Revision tags: v9.2.0, v9.1.2, v9.1.1 |
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#
28ae3179 |
| 13-Sep-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-target-arm-20240913' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * s390: convert s390 virtio-ccw and CPU to three-phase reset * reset: remove
Merge tag 'pull-target-arm-20240913' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * s390: convert s390 virtio-ccw and CPU to three-phase reset * reset: remove now-unused device_class_set_parent_reset() * reset: introduce device_class_set_legacy_reset() * reset: remove unneeded transitional machinery * kvm: Use 'unsigned long' for request argument in functions wrapping ioctl() * hvf: arm: Implement and use hvf_get_physical_address_range so VMs can have larger-than-36-bit IPA spaces when the host supports this * target/arm/tcg: refine cache descriptions with a wrapper * hw/net/can/xlnx-versal-canfd: fix various bugs * MAINTAINERS: update versal, CAN maintainer entries * hw/intc/arm_gic: fix spurious level triggered interrupts
# -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmbkVokZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pR5D/0ZJzJi7C0HIa4KYuBkcpZQ # M3iUa1uiZoCniXlWuKFt2rUBrmhbW30YHw5gQjnxoUO4VVqREkFi3e5nzUKRQmvP # FRm8dnuC36qwQJFhm+rQqUb8/AyqrVFnIaHhn7dBKLwRFm9+kbZ0v9x1Eq1DZk3S # mijBQRiOjrj+FRkmyNJLhylGpm+p9VRdnBjmUtN2Yw+2fPkHmUURRSUvhwCK4BB5 # AvKgMC0EIIsLJKLfrWzk/EsYC8ogrGitISzFt8iWLAqxuxtuhv1StstleD4mZMK8 # gH+ZH5tsls2IiTIKkHfcbUcA55efDrQHGDat7n1Q0EWqOjET0soES+GpS0Jj6IXK # uOnsDZ7MLFU/SbpckicLQ/JwNi3HiIfQgBVB2aJZ+cg8CGqaQCI5ZvWs7XFpUgkb # naA4IR5mdNgXJm7ttBKbWarPNcmdODqa/5YDjXdyHmMx3JD994k1y5LIi3o69TgI # rgHzU8ChZqaBDEvNa5KGtadQPnaSBP15Yqbp5rn2knVRKjDdyCdB94aWO5tZkmaO # ARFmNk6h5bhwXdXl2Hu67RS2Kd0/fHMFWsxyHAX4NYT+Vq+ZTjLdaPzwFdfA0yAz # wXWn0EAeYQ5M2xOPfDM/JYSc1THSzhpwy/CBrRjrCRZMDE+bx9BRC7pUXwquE8xF # CW1NUxkvZikQeiMzgEBbTA== # =u6u8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 13 Sep 2024 16:13:13 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20240913' of https://git.linaro.org/people/pmaydell/qemu-arm: (27 commits) hw/intc/arm_gic: fix spurious level triggered interrupts MAINTAINERS: Add my-self as CAN maintainer MAINTAINERS: Update Xilinx Versal OSPI maintainer's email address MAINTAINERS: Remove Vikram Garhwal as maintainer hw/net/can/xlnx-versal-canfd: Fix FIFO issues hw/net/can/xlnx-versal-canfd: Simplify DLC conversions hw/net/can/xlnx-versal-canfd: Fix byte ordering hw/net/can/xlnx-versal-canfd: Handle flags correctly hw/net/can/xlnx-versal-canfd: Translate CAN ID registers hw/net/can/xlnx-versal-canfd: Fix CAN FD flag check hw/net/can/xlnx-versal-canfd: Fix interrupt level target/arm/tcg: refine cache descriptions with a wrapper hvf: arm: Implement and use hvf_get_physical_address_range hvf: Split up hv_vm_create logic per arch hw/boards: Add hvf_get_physical_address_range to MachineClass kvm: Use 'unsigned long' for request argument in functions wrapping ioctl() hw/core/resettable: Remove transitional_function machinery hw/core/qdev: Simplify legacy_reset handling hw: Remove device_phases_reset() hw: Rename DeviceClass::reset field to legacy_reset ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
e3d08143 |
| 13-Sep-2024 |
Peter Maydell <peter.maydell@linaro.org> |
hw: Use device_class_set_legacy_reset() instead of opencoding
Use device_class_set_legacy_reset() instead of opencoding an assignment to DeviceClass::reset. This change was produced with: spatch --
hw: Use device_class_set_legacy_reset() instead of opencoding
Use device_class_set_legacy_reset() instead of opencoding an assignment to DeviceClass::reset. This change was produced with: spatch --macro-file scripts/cocci-macro-file.h \ --sp-file scripts/coccinelle/device-reset.cocci \ --keep-comments --smpl-spacing --in-place --dir hw
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240830145812.1967042-8-peter.maydell@linaro.org
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Revision tags: v9.1.0 |
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#
d328fef9 |
| 04-Jan-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-20231230' of https://gitlab.com/rth7680/qemu into staging
Mark VMStateField and VMStateDescription arrays const.
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXA
Merge tag 'pull-20231230' of https://gitlab.com/rth7680/qemu into staging
Mark VMStateField and VMStateDescription arrays const.
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmWPOFsdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8cCQgAnQjy3Ic1i225AElh # 0Ph3Aiw6WT9pECLoKmyroxHbTGuaEJoIXeaOhMAnowCTBLoKRR3/Ooq0DGOW+l/Z # f5PwWSkjkb+OcS+dj/kgQBu58/Gk5G8ogksqKQvci8k2okhjHmITSQDu0dtwzDZr # jVGh3gmGoat73jQyD/nAwgWFawlLkklOMR/yvnFX7EJIBepRVbkMPayoKlB+6W07 # 1kqhSwoI0vQCjhJ3Q7Q0GC4rrHK3KUq7o/25yvICf4EgPKfsaym1wAjDhdKToixl # 9T+ALZG8SiZZkBlb6l3QZ7pqtqavxYtPdZ2Gx/nMu0RRu4G33d5AVGHRrXj9qttW # 5mL7ZQ== # =uQ4C # -----END PGP SIGNATURE----- # gpg: Signature made Fri 29 Dec 2023 21:21:31 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-20231230' of https://gitlab.com/rth7680/qemu: (71 commits) docs: Constify VMstate in examples tests/unit/test-vmstate: Constify VMState util/fifo8: Constify VMState replay: Constify VMState system: Constify VMState migration: Constify VMState cpu-target: Constify VMState backends: Constify VMState audio: Constify VMState hw/misc/macio: Constify VMState hw/watchdog: Constify VMState hw/virtio: Constify VMState hw/vfio: Constify VMState hw/usb: Constify VMState hw/tpm: Constify VMState hw/timer: Constify VMState hw/ssi: Constify VMState hw/sparc: Constify VMState hw/sensor: Constify VMState hw/sd: Constify VMState ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
307119ba |
| 20-Dec-2023 |
Richard Henderson <richard.henderson@linaro.org> |
hw/sd: Constify VMState
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
hw/sd: Constify VMState
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-53-richard.henderson@linaro.org>
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#
ed1d873c |
| 07-Nov-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'misc-cpus-20231107' of https://github.com/philmd/qemu into staging
Misc hardware patch queue
HW emulation: - PMBus fixes and tests (Titus) - IDE fixes and tests (Fiona) - New ADM1266 sen
Merge tag 'misc-cpus-20231107' of https://github.com/philmd/qemu into staging
Misc hardware patch queue
HW emulation: - PMBus fixes and tests (Titus) - IDE fixes and tests (Fiona) - New ADM1266 sensor (Titus) - Better error propagation in PCI-ISA i82378 (Philippe) - Declare SD model QOM types using DEFINE_TYPES macro (Philippe)
Topology: - Fix CPUState::nr_cores calculation (Zhuocheng Ding and Zhao Liu)
Monitor: - Synchronize CPU state in 'info lapic' (Dongli Zhang)
QOM: - Have 'cpu-qom.h' target-agnostic (Philippe) - Move ArchCPUClass definition to each target's cpu.h (Philippe) - Call object_class_is_abstract once in cpu_class_by_name (Philippe)
UI: - Use correct key names in titles on MacOS / SDL2 (Adrian)
MIPS: - Fix MSA BZ/BNZ and TX79 LQ/SQ opcodes (Philippe)
Nios2: - Create IRQs *after* vCPU is realized (Philippe)
PPC: - Restrict KVM objects to system emulation (Philippe) - Move target-specific definitions out of 'cpu-qom.h' (Philippe)
S390X: - Make hw/s390x/css.h and hw/s390x/sclp.h headers target agnostic (Philippe)
X86: - HVF & KVM cleanups (Philippe)
Various targets: - Use env_archcpu() to optimize (Philippe)
Misc: - Few global variable shadowing removed (Philippe) - Introduce cpu_exec_reset_hold and factor tcg_cpu_reset_hold out (Philippe) - Remove few more 'softmmu' mentions (Philippe) - Fix and cleanup in vl.c (Akihiko & Marc-André) - Resource leak fix in dump (Zongmin Zhou) - MAINTAINERS updates (Thomas, Daniel)
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmVKKmEACgkQ4+MsLN6t # wN4xHQ//X/enH4C7K3VP/tSinDiwmXN2o61L9rjqSDQkBaCtktZx4c8qKSDL7V4S # vwzmvvBn3biMXQwZNVJo9d0oz2qoaF9tI6Ao0XDHAan9ziagfG9YMqWhkCfj077Q # jLdCqkUuMJBvQgXGB1a6UgCme8PQx7h0oqjbCNfB0ZBls24b5DiEjO87LE4OTbTi # zKRhYEpZpGwIVcy+1dAsbaBpGFP06sr1doB9Wz4c06eSx7t0kFSPk6U4CyOPrGXh # ynyCxPwngxIXmarY8gqPs3SBs7oXsH8Q/ZOHr1LbuXhwSuw/0zBQU9aF7Ir8RPan # DB79JjPrtxTAhICKredWT79v9M18D2/1MpONgg4vtx5K2FzGYoAJULCHyfkHMRSM # L6/H0ZQPHvf7w72k9EcSQIhd0wPlMqRmfy37/8xcLiw1h4l/USx48QeKaeFWeSEu # DgwSk+R61HbrKvQz/U0tF98zUEyBaQXNrKmyzht0YE4peAtpbPNBeRHkd0GMae/Z # HOmkt8QlFQ0T14qSK7mSHaSJTUzRvFGD01cbuCDxVsyCWWsesEikXBACZLG5RCRY # Rn1WeX1H9eE3kKi9iueLnhzcF9yM5XqFE3f6RnDzY8nkg91lsTMSQgFcIpv6uGyp # 3WOTNSC9SoFyI3x8pCWiKOGytPUb8xk+PnOA85wYvVmT+7j6wus= # =OVdQ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 20:15:29 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'misc-cpus-20231107' of https://github.com/philmd/qemu: (75 commits) dump: Add close fd on error return to avoid resource leak ui/sdl2: use correct key names in win title on mac MAINTAINERS: Add more guest-agent related files to the corresponding section MAINTAINERS: Add include/hw/xtensa/mx_pic.h to the XTFPGA machine section MAINTAINERS: update libvirt devel mailing list address MAINTAINERS: Add the CAN documentation file to the CAN section MAINTAINERS: Add include/hw/timer/tmu012.h to the SH4 R2D section hw/sd: Declare QOM types using DEFINE_TYPES() macro hw/i2c: pmbus: reset page register for out of range reads hw/i2c: pmbus: immediately clear faults on request tests/qtest: add tests for ADM1266 hw/sensor: add ADM1266 device model hw/i2c: pmbus: add VCAP register hw/i2c: pmbus: add fan support hw/i2c: pmbus: add vout mode bitfields hw/i2c: pmbus add support for block receive tests/qtest: ahci-test: add test exposing reset issue with pending callback hw/ide: reset: cancel async DMA operation before resetting state hw/cpu: Update the comments of nr_cores and nr_dies system/cpus: Fix CPUState.nr_cores' calculation ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
88d2198c |
| 31-Oct-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/sd: Declare QOM types using DEFINE_TYPES() macro
When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array decla
hw/sd: Declare QOM types using DEFINE_TYPES() macro
When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review.
Mechanical transformation using the following comby script:
[pattern-x1] match=''' static const TypeInfo :[i1~.*_info] = { :[body] }; static void :[rt1~.*_register_type.](void) { type_register_static(&:[i2~.*_info]); } type_init(:[rt2~.*_register_type.]) ''' rewrite=''' static const TypeInfo :[i1][] = { { :[body] }, };
DEFINE_TYPES(:[i1]) ''' rule='where :[i1] == :[i2], :[rt1] == :[rt2]'
[pattern-x2] match=''' static const TypeInfo :[i1a~.*_info] = { :[body1] }; ... static const TypeInfo :[i2a~.*_info] = { :[body2] }; static void :[rt1~.*_register_type.](void) { type_register_static(&:[i1b~.*_info]); type_register_static(&:[i2b~.*_info]); } type_init(:[rt2~.*_register_type.]) ''' rewrite=''' static const TypeInfo :[i1a][] = { { :[body1] }, { :[body2] }, };
DEFINE_TYPES(:[i1a]) ''' rule=''' where :[i1a] == :[i1b], :[i2a] == :[i2b], :[rt1] == :[rt2] '''
and re-indented manually.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20231031080603.86889-2-philmd@linaro.org>
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Revision tags: v8.0.0, v7.2.0, v7.0.0 |
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#
e630bc7e |
| 15-Dec-2021 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-block-2021-12-15' of git://repo.or.cz/qemu/armbru into staging
Block device patches patches for 2021-12-15
# gpg: Signature made Wed 15 Dec 2021 05:58:14 AM PST # gpg:
Merge tag 'pull-block-2021-12-15' of git://repo.or.cz/qemu/armbru into staging
Block device patches patches for 2021-12-15
# gpg: Signature made Wed 15 Dec 2021 05:58:14 AM PST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full]
* tag 'pull-block-2021-12-15' of git://repo.or.cz/qemu/armbru: blockdev: Drop unused drive_get_next() hw/arm/aspeed: Replace drive_get_next() by drive_get() hw/arm/xilinx_zynq: Replace drive_get_next() by drive_get() hw/arm/xlnx-zcu102: Replace drive_get_next() by drive_get() hw/microblaze: Replace drive_get_next() by drive_get() hw/arm/xlnx-versal-virt: Replace drive_get_next() by drive_get() hw/arm/mcimx7d-sabre: Replace drive_get_next() by drive_get() hw/arm/mcimx6ul-evk: Replace drive_get_next() by drive_get() hw/arm/imx25_pdk: Replace drive_get_next() by drive_get() hw/arm/versatilepb hw/arm/vexpress: Replace drive_get_next() by drive_get() hw/arm/npcm7xx_boards: Replace drive_get_next() by drive_get() hw: Replace trivial drive_get_next() by drive_get() hw/sd/ssi-sd: Do not create SD card within controller's realize
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v6.2.0 |
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36aa285f |
| 17-Nov-2021 |
Markus Armbruster <armbru@redhat.com> |
hw/sd/ssi-sd: Do not create SD card within controller's realize
ssi_sd_realize() creates an "sd-card" device. This is inappropriate, and marked FIXME.
Move it to the boards that create these devic
hw/sd/ssi-sd: Do not create SD card within controller's realize
ssi_sd_realize() creates an "sd-card" device. This is inappropriate, and marked FIXME.
Move it to the boards that create these devices. Prior art: commit eb4f566bbb for device "generic-sdhci", and commit 26c607b86b for device "pl181".
The device remains not user-creatable, because its users should (and do) wire up its GPIO chip-select line.
Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Bin Meng <bin.meng@windriver.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> Cc: qemu-arm@nongnu.org Cc: qemu-riscv@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20211117163409.3587705-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
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#
bb4aa8f5 |
| 30-Sep-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210930' into staging
target-arm queue: * allwinner-h3: Switch to SMC as PSCI conduit * arm: tcg: Adhere to SMCCC 1.3 section 5
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210930' into staging
target-arm queue: * allwinner-h3: Switch to SMC as PSCI conduit * arm: tcg: Adhere to SMCCC 1.3 section 5.2 * xlnx-zcu102, xlnx-versal-virt: Support BBRAM and eFUSE devices * gdbstub related code cleanups * Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML * Use _init vs _new convention in bus creation function names * sabrelite: Connect SPI flash CS line to GPIO3_19
# gpg: Signature made Thu 30 Sep 2021 16:11:20 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210930: (22 commits) hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 ide: Rename ide_bus_new() to ide_bus_init() qbus: Rename qbus_create() to qbus_new() qbus: Rename qbus_create_inplace() to qbus_init() pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init() ipack: Rename ipack_bus_new_inplace() to ipack_bus_init() scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named() target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML target/arm: Move gdbstub related code out of helper.c target/arm: Fix coding style issues in gdbstub code in helper.c configs: Don't include 32-bit-only GDB XML in aarch64 linux configs docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage hw/arm: xlnx-zcu102: Add Xilinx eFUSE device hw/arm: xlnx-zcu102: Add Xilinx BBRAM device hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device hw/nvram: Introduce Xilinx battery-backed ram hw/nvram: Introduce Xilinx ZynqMP eFuse device hw/nvram: Introduce Xilinx Versal eFuse device hw/nvram: Introduce Xilinx eFuse QOM ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
d637e1dc |
| 23-Sep-2021 |
Peter Maydell <peter.maydell@linaro.org> |
qbus: Rename qbus_create_inplace() to qbus_init()
Rename qbus_create_inplace() to qbus_init(); this is more in line with our usual naming convention for functions that in-place initialize objects.
qbus: Rename qbus_create_inplace() to qbus_init()
Rename qbus_create_inplace() to qbus_init(); this is more in line with our usual naming convention for functions that in-place initialize objects.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20210923121153.23754-5-peter.maydell@linaro.org
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Revision tags: v6.1.0 |
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a528b8c4 |
| 20-Feb-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sdmmc-20210220' into staging
SD/MMC patches
- Various improvements for SD cards in SPI mode (Bin Meng) - Add Bin Meng as SD/MMC cards co-mai
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sdmmc-20210220' into staging
SD/MMC patches
- Various improvements for SD cards in SPI mode (Bin Meng) - Add Bin Meng as SD/MMC cards co-maintainer
# gpg: Signature made Sat 20 Feb 2021 00:09:44 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/sdmmc-20210220: MAINTAINERS: Add Bin Meng as co-maintainer for SD/MMC cards hw/sd: sdhci: Simplify updating s->prnsts in sdhci_sdma_transfer_multi_blocks() hw/sd: sd: Bypass the RCA check for CMD13 in SPI mode hw/sd: sd: Skip write protect groups check in CMD24/25 for high capacity cards hw/sd: sd: Skip write protect groups check in sd_erase() for high capacity cards hw/sd: sd: Move the sd_block_{read, write} and macros ahead hw/sd: sd: Fix CMD30 response type hw/sd: sd: Only SDSC cards support CMD28/29/30 hw/sd: sd: Fix address check in sd_erase() hw/sd: ssi-sd: Handle the rest commands with R1b response type hw/sd: ssi-sd: Fix STOP_TRANSMISSION (CMD12) response hw/sd: ssi-sd: Fix SEND_IF_COND (CMD8) response hw/sd: ssi-sd: Support multiple block write hw/sd: ssi-sd: Support single block write hw/sd: Introduce receive_ready() callback hw/sd: sd: Allow single/multiple block write for SPI mode hw/sd: sd: Remove duplicated codes in single/multiple block read/write hw/sd: ssi-sd: Support multiple block read
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
17674695 |
| 28-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/sd: ssi-sd: Handle the rest commands with R1b response type
Besides CMD12, the following command's reponse type is R1b:
- SET_WRITE_PROT (CMD28) - CLR_WRITE_PROT (CMD29) - ERASE (CMD38)
Reuse t
hw/sd: ssi-sd: Handle the rest commands with R1b response type
Besides CMD12, the following command's reponse type is R1b:
- SET_WRITE_PROT (CMD28) - CLR_WRITE_PROT (CMD29) - ERASE (CMD38)
Reuse the same s->stopping to indicate a R1b reponse is needed.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210128063035.15674-10-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
5b45a366 |
| 28-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/sd: ssi-sd: Fix STOP_TRANSMISSION (CMD12) response
CMD12's response type is R1b, which is basically a R1 plus optional addition of the busy signal token that can be any number of bytes. A zero va
hw/sd: ssi-sd: Fix STOP_TRANSMISSION (CMD12) response
CMD12's response type is R1b, which is basically a R1 plus optional addition of the busy signal token that can be any number of bytes. A zero value indicates card is busy and a non-zero value indicates the card is ready for the next command.
Current implementation sends the busy signal token without sending the R1 first. This does not break the U-Boot/Linux mmc_spi driver, but it does not make the VxWorks driver happy.
Move the testing logic of s->stopping in the SSI_SD_RESPONSE state a bit later, after the first byte of the card reponse is sent out, to conform with the spec. After the busy signal token is sent, the state should be transferred to SSI_SD_CMD.
Fixes: 775616c3ae8c ("Partial SD card SPI mode support") Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20210128063035.15674-9-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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6ae29af3 |
| 28-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/sd: ssi-sd: Fix SEND_IF_COND (CMD8) response
The SEND_IF_COND command (CMD8) response is of format R7, but current code returns R1 for CMD8. Fix it.
Fixes: 775616c3ae8c ("Partial SD card SPI mod
hw/sd: ssi-sd: Fix SEND_IF_COND (CMD8) response
The SEND_IF_COND command (CMD8) response is of format R7, but current code returns R1 for CMD8. Fix it.
Fixes: 775616c3ae8c ("Partial SD card SPI mode support") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210128063035.15674-8-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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d56f3efa |
| 28-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/sd: ssi-sd: Support multiple block write
For a multiple block write operation, each block begins with a multi write start token. Unlike the SD mode that the multiple block write ends when receivi
hw/sd: ssi-sd: Support multiple block write
For a multiple block write operation, each block begins with a multi write start token. Unlike the SD mode that the multiple block write ends when receiving a STOP_TRAN command (CMD12), a special stop tran token is used to signal the card.
Emulating this by manually sending a CMD12 to the SD card core, to bring it out of the receiving data state.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210128063035.15674-7-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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5020e3cb |
| 28-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/sd: ssi-sd: Support single block write
Add 2 more states for the block write operation. The SPI host needs to send a data start token to start the transfer, and the data block written to the card
hw/sd: ssi-sd: Support single block write
Add 2 more states for the block write operation. The SPI host needs to send a data start token to start the transfer, and the data block written to the card will be acknowledged by a data response token.
Signed-off-by: Bin Meng <bin.meng@windriver.com> [PMD: Change VMState version id 6 -> 7] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210128063035.15674-6-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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1365d863 |
| 28-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/sd: ssi-sd: Support multiple block read
In the case of a multiple block read operation every transferred block has its suffix of CRC16. Update the state machine logic to handle multiple block rea
hw/sd: ssi-sd: Support multiple block read
In the case of a multiple block read operation every transferred block has its suffix of CRC16. Update the state machine logic to handle multiple block read.
Signed-off-by: Bin Meng <bin.meng@windriver.com> [PMD: Change VMState version id 5 -> 6] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210128063035.15674-2-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
55d98950 |
| 25-Jan-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sdmmc-20210124' into staging
SD/MMC patches
- Various improvements for SD cards in SPI mode (Bin Meng)
# gpg: Signature made Sun 24 Jan 202
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sdmmc-20210124' into staging
SD/MMC patches
- Various improvements for SD cards in SPI mode (Bin Meng)
# gpg: Signature made Sun 24 Jan 2021 19:16:55 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* remotes/philmd-gitlab/tags/sdmmc-20210124: hw/sd: sd.h: Cosmetic change of using spaces hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION hw/sd: ssi-sd: Add a state representing Nac hw/sd: ssi-sd: Suffix a data block with CRC16 util: Add CRC16 (CCITT) calculation routines hw/sd: sd: Drop sd_crc16() hw/sd: sd: Support CMD59 for SPI mode hw/sd: ssi-sd: Fix incorrect card response sequence
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
bc1edaf2 |
| 23-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer
At present the codes use hardcoded numbers (0xff/0xfe) for the dummy value and block start token. Replace them with macros.
hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer
At present the codes use hardcoded numbers (0xff/0xfe) for the dummy value and block start token. Replace them with macros.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210123104016.17485-12-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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1fb85c42 |
| 23-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION
This fixes the wrong command index for STOP_TRANSMISSION, the required command to interrupt the multiple block read command, in the o
hw/sd: ssi-sd: Fix the wrong command index for STOP_TRANSMISSION
This fixes the wrong command index for STOP_TRANSMISSION, the required command to interrupt the multiple block read command, in the old codes. It should be CMD12 (0x4c), not CMD13 (0x4d).
Fixes: 775616c3ae8c ("Partial SD card SPI mode support") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210123104016.17485-10-bmeng.cn@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
3a67cbe6 |
| 23-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/sd: ssi-sd: Add a state representing Nac
Per the "Physical Layer Specification Version 8.00" chapter 7.5.2, "Data Read", there is a minimum 8 clock cycles (Nac) after the card response and before
hw/sd: ssi-sd: Add a state representing Nac
Per the "Physical Layer Specification Version 8.00" chapter 7.5.2, "Data Read", there is a minimum 8 clock cycles (Nac) after the card response and before data block shows up on the data out line. This applies to both single and multiple block read operations.
Current implementation of single block read already satisfies the timing requirement as in the RESPONSE state after all responses are transferred the state remains unchanged. In the next 8 clock cycles it jumps to DATA_START state if data is ready.
However we need an explicit state when expanding our support to multiple block read in the future. Let's add a new state PREP_DATA explicitly in the ssi-sd state machine to represent Nac.
Note we don't change the single block read state machine to let it jump from RESPONSE state to DATA_START state as that effectively generates a 16 clock cycles Nac, which might not be safe. As the spec says the maximum Nac shall be calculated from several fields encoded in the CSD register, we don't want to bother updating CSD to ensure our Nac is within range to complicate things.
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210123104016.17485-9-bmeng.cn@gmail.com> [PMD: Change VMState version id 4 -> 5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
2d174cc3 |
| 23-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/sd: ssi-sd: Suffix a data block with CRC16
Per the SD spec, a valid data block is suffixed with a 16-bit CRC generated by the standard CCITT polynomial x16+x12+x5+1. This part is currently missin
hw/sd: ssi-sd: Suffix a data block with CRC16
Per the SD spec, a valid data block is suffixed with a 16-bit CRC generated by the standard CCITT polynomial x16+x12+x5+1. This part is currently missing in the ssi-sd state machine. Without it, all data block transfer fails in guest software because the expected CRC16 is missing on the data out line.
Fixes: 775616c3ae8c ("Partial SD card SPI mode support") Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210123104016.17485-8-bmeng.cn@gmail.com> [PMD: Change VMState version id 3 -> 4, check s->mode validity in post_load()] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
281c5c95 |
| 23-Jan-2021 |
Bin Meng <bin.meng@windriver.com> |
hw/sd: ssi-sd: Fix incorrect card response sequence
Per the "Physical Layer Specification Version 8.00" chapter 7.5.1, "Command/Response", there is a minimum 8 clock cycles (Ncr) before the card res
hw/sd: ssi-sd: Fix incorrect card response sequence
Per the "Physical Layer Specification Version 8.00" chapter 7.5.1, "Command/Response", there is a minimum 8 clock cycles (Ncr) before the card response shows up on the data out line. However current implementation jumps directly to the sending response state after all 6 bytes command is received, which is a spec violation.
Add a new state PREP_RESP in the ssi-sd state machine to handle it.
Fixes: 775616c3ae8c ("Partial SD card SPI mode support") Signed-off-by: Bin Meng <bin.meng@windriver.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210123104016.17485-4-bmeng.cn@gmail.com> [PMD: Change VMState version id 2 -> 3] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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#
b785d25e |
| 11-Dec-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging
* Fix for NULL segments (Bin Meng) * Support for 32768 CPUs on x86 without IOMMU (David) * PDEP/PEXT fix and test
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging
* Fix for NULL segments (Bin Meng) * Support for 32768 CPUs on x86 without IOMMU (David) * PDEP/PEXT fix and testcase (myself) * Remove bios_name and ram_size globals (myself) * qemu_init rationalization (myself) * Update kernel-doc (myself + upstream patches) * Propagate MemTxResult across DMA and PCI functions (Philippe) * Remove master/slave when applicable (Philippe) * WHPX support for in-kernel irqchip (Sunil)
# gpg: Signature made Thu 10 Dec 2020 17:21:50 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini-gitlab/tags/for-upstream: (113 commits) scripts: kernel-doc: remove unnecessary change wrt Linux Revert "docs: temporarily disable the kernel-doc extension" scripts: kernel-doc: use :c:union when needed scripts: kernel-doc: split typedef complex regex scripts: kernel-doc: fix typedef parsing Revert "kernel-doc: Handle function typedefs that return pointers" Revert "kernel-doc: Handle function typedefs without asterisks" scripts: kernel-doc: try to use c:function if possible scripts: kernel-doc: fix line number handling scripts: kernel-doc: allow passing desired Sphinx C domain dialect scripts: kernel-doc: don't mangle with parameter list scripts: kernel-doc: fix typedef identification scripts: kernel-doc: reimplement -nofunction argument scripts: kernel-doc: fix troubles with line counts scripts: kernel-doc: use a less pedantic markup for funcs on Sphinx 3.x scripts: kernel-doc: make it more compatible with Sphinx 3.x Revert "kernel-doc: Use c:struct for Sphinx 3.0 and later" Revert "scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments" scripts: kernel-doc: add support for typedef enum kernel-doc: add support for ____cacheline_aligned attribute ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v5.2.0 |
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ec7e429b |
| 12-Oct-2020 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
hw/ssi: Rename SSI 'slave' as 'peripheral'
In order to use inclusive terminology, rename SSI 'slave' as 'peripheral', following the specification resolution: https://www.oshwa.org/a-resolution-to-re
hw/ssi: Rename SSI 'slave' as 'peripheral'
In order to use inclusive terminology, rename SSI 'slave' as 'peripheral', following the specification resolution: https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
Patch created mechanically using:
$ sed -i s/SSISlave/SSIPeripheral/ $(git grep -l SSISlave) $ sed -i s/SSI_SLAVE/SSI_PERIPHERAL/ $(git grep -l SSI_SLAVE) $ sed -i s/ssi-slave/ssi-peripheral/ $(git grep -l ssi-slave) $ sed -i s/ssi_slave/ssi_peripheral/ $(git grep -l ssi_slave) $ sed -i s/ssi_create_slave/ssi_create_peripheral/ \ $(git grep -l ssi_create_slave)
Then in VMStateDescription vmstate_ssi_peripheral we restored the "SSISlave" migration stream name (to avoid breaking migration).
Finally the following files have been manually tweaked: - hw/ssi/pl022.c - hw/ssi/xilinx_spips.c
Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012124955.3409127-4-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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