History log of /openbmc/qemu/hw/ppc/pnv_i2c.c (Results 1 – 11 of 11)
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Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0
# 7e9595e4 19-Mar-2024 Peter Maydell <peter.maydell@linaro.org>

Merge tag 'pull-for-9.0-20240319' of https://github.com/legoater/qemu into staging

aspeed, pnv, vfio queue:

* user device fixes for Aspeed and PowerNV machines
* coverity fix for iommufd

# -----BE

Merge tag 'pull-for-9.0-20240319' of https://github.com/legoater/qemu into staging

aspeed, pnv, vfio queue:

* user device fixes for Aspeed and PowerNV machines
* coverity fix for iommufd

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# gpg: Signature made Tue 19 Mar 2024 14:00:13 GMT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1

* tag 'pull-for-9.0-20240319' of https://github.com/legoater/qemu:
aspeed/smc: Only wire flash devices at reset
ppc/pnv: I2C controller is not user creatable
vfio/iommufd: Fix memory leak

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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# 5b2b9450 18-Mar-2024 Cédric Le Goater <clg@redhat.com>

ppc/pnv: I2C controller is not user creatable

The I2C controller is a subunit of the processor. Make it so and avoid
QEMU crashes.

$ build/qemu-system-ppc64 -S -machine powernv9 -device pnv-i2c

ppc/pnv: I2C controller is not user creatable

The I2C controller is a subunit of the processor. Make it so and avoid
QEMU crashes.

$ build/qemu-system-ppc64 -S -machine powernv9 -device pnv-i2c
qemu-system-ppc64: ../hw/ppc/pnv_i2c.c:521: pnv_i2c_realize: Assertion `i2c->chip' failed.
Aborted (core dumped)

Fixes: 263b81ee15af ("ppc/pnv: Add an I2C controller model")
Cc: Glenn Miles <milesg@linux.vnet.ibm.com>
Reported-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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# 91e3bf2e 23-Feb-2024 Peter Maydell <peter.maydell@linaro.org>

Merge tag 'pull-ppc-for-9.0-20240224' of https://gitlab.com/npiggin/qemu into staging

* Avocado tests for ppc64 to boot FreeBSD, run guests with emulated
or nested hypervisor facilities, among oth

Merge tag 'pull-ppc-for-9.0-20240224' of https://gitlab.com/npiggin/qemu into staging

* Avocado tests for ppc64 to boot FreeBSD, run guests with emulated
or nested hypervisor facilities, among other things.
* Update ppc64 CPU defaults to Power10.
* Add a new powernv10-rainier machine to better capture differences
between the different Power10 systems.
* Implement more device models for powernv.
* 4xx TLB flushing performance and correctness improvements.
* Correct gdb implementation to access some important SPRs.
* Misc cleanups and bug fixes.

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# gpg: Signature made Fri 23 Feb 2024 15:27:57 GMT
# gpg: using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE
# gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0 A795 67B3 0276 A862 1CAE

* tag 'pull-ppc-for-9.0-20240224' of https://gitlab.com/npiggin/qemu: (47 commits)
target/ppc: optimise ppcemb_tlb_t flushing
target/ppc: 440 optimise tlbwe TLB flushing
target/ppc: 4xx optimise tlbwe_lo TLB flushing
target/ppc: 4xx don't flush TLB for a newly written software TLB entry
target/ppc: Factor out 4xx ppcemb_tlb_t flushing
target/ppc: Fix 440 tlbwe TLB invalidation gaps
target/ppc: Add SMT support to time facilities
target/ppc: Implement core timebase state machine and TFMR
ppc/pnv: Implement the ChipTOD to Core transfer
ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines
ppc/pnv: Add POWER9/10 chiptod model
target/ppc: Fix move-to timebase SPR access permissions
target/ppc: Improve timebase register defines naming
target/ppc: Rename TBL to TB on 64-bit
target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U
hw/ppc: N1 chiplet wiring
hw/ppc: Add N1 chiplet model
hw/ppc: Add pnv nest pervasive common chiplet model
ppc/pnv: Test pnv i2c master and connected devices
ppc/pnv: Add a pca9554 I2C device to powernv10-rainier
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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# 4d2cd2d8 05-Feb-2024 Glenn Miles <milesg@linux.vnet.ibm.com>

ppc/pnv: Test pnv i2c master and connected devices

Tests the following for both P9 and P10:
- I2C master POR status
- I2C master status after immediate reset

Tests the following for powernv10-r

ppc/pnv: Test pnv i2c master and connected devices

Tests the following for both P9 and P10:
- I2C master POR status
- I2C master status after immediate reset

Tests the following for powernv10-ranier only:
- Config pca9552 hotplug device pins as inputs then
Read the INPUT0/1 registers to verify all pins are high
- Connected GPIO pin tests of P10 PCA9552 device. Tests
output of pins 0-4 affect input of pins 5-9 respectively.
- PCA9554 GPIO pins test. Tests input and ouput functionality.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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# 7b85f008 05-Feb-2024 Glenn Miles <milesg@linux.vnet.ibm.com>

ppc/pnv: Use resettable interface to reset child I2C buses

The QEMU I2C buses and devices use the resettable
interface for resetting while the PNV I2C controller
and parent buses and devices have no

ppc/pnv: Use resettable interface to reset child I2C buses

The QEMU I2C buses and devices use the resettable
interface for resetting while the PNV I2C controller
and parent buses and devices have not yet transitioned
to this new interface and use the old reset strategy.
This was preventing the I2C buses and devices wired
to the PNV I2C controller from being reset.

The short term fix for this is to have the PNV I2C
Controller's reset function explicitly call the resettable
interface function, bus_cold_reset(), on all child
I2C buses.

The long term fix should be to transition all PNV parent
devices and buses to use the resettable interface so that
all child buses and devices are automatically reset.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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# adf798b3 21-Nov-2023 Stefan Hajnoczi <stefanha@redhat.com>

Merge tag 'pull-ppc-20231121' of https://github.com/legoater/qemu into staging

ppc queue:

* PNV I2C fixes
* VSX instruction fix when converting floating point to integer values

# -----BEGIN PGP SI

Merge tag 'pull-ppc-20231121' of https://github.com/legoater/qemu into staging

ppc queue:

* PNV I2C fixes
* VSX instruction fix when converting floating point to integer values

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# gpg: Signature made Tue 21 Nov 2023 03:16:31 EST
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [unknown]
# gpg: aka "Cédric Le Goater <clg@kaod.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1

* tag 'pull-ppc-20231121' of https://github.com/legoater/qemu:
ppc/pnv: Fix PNV I2C invalid status after reset
ppc/pnv: PNV I2C engines assigned incorrect XSCOM addresses
target/ppc: Fix bugs in VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2 macros
ppc/pnv: Fix potential overflow in I2C model

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

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# b664466d 14-Nov-2023 Glenn Miles <milesg@linux.vnet.ibm.com>

ppc/pnv: Fix PNV I2C invalid status after reset

The PNV I2C Controller was clearing the status register
after a reset without repopulating the "upper threshold
for I2C ports", "Command Complete" and

ppc/pnv: Fix PNV I2C invalid status after reset

The PNV I2C Controller was clearing the status register
after a reset without repopulating the "upper threshold
for I2C ports", "Command Complete" and the SCL/SDA input
level fields.

Fixed this for resets caused by a system reset as well
as from writing to the "Immediate Reset" register.

Fixes: 263b81ee15af ("ppc/pnv: Add an I2C controller model")
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 47dfdd23 14-Nov-2023 Glenn Miles <milesg@linux.vnet.ibm.com>

ppc/pnv: PNV I2C engines assigned incorrect XSCOM addresses

The PNV I2C engines for power9 and power10 were being assigned a base
XSCOM address that was off by one I2C engine's address range such
th

ppc/pnv: PNV I2C engines assigned incorrect XSCOM addresses

The PNV I2C engines for power9 and power10 were being assigned a base
XSCOM address that was off by one I2C engine's address range such
that engine 0 had engine 1's address and so on. The xscom address
assignment was being based on the device tree engine numbering, which
starts at 1. Rather than changing the device tree numbering to start
with 0, the addressing was changed to be based on the existing device
tree numbers minus one.

Fixes: 1ceda19c28a1 ("ppc/pnv: Connect PNV I2C controller to powernv10)
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# 8bc5ae04 09-Nov-2023 Cédric Le Goater <clg@kaod.org>

ppc/pnv: Fix potential overflow in I2C model

Coverity warns that "i2c_bus_busy(i2c->busses[i]) << i" might overflow
because the expression is evaluated using 32-bit arithmetic and then
used in a con

ppc/pnv: Fix potential overflow in I2C model

Coverity warns that "i2c_bus_busy(i2c->busses[i]) << i" might overflow
because the expression is evaluated using 32-bit arithmetic and then
used in a context expecting a uint64_t.

While we are at it, introduce a PNV_I2C_MAX_BUSSES constant and check
the number of busses at realize time.

Fixes: Coverity CID 1523918
Cc: Glenn Miles <milesg@linux.vnet.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>

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# a3c3aaa8 08-Nov-2023 Stefan Hajnoczi <stefanha@redhat.com>

Merge tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu into staging

ppc patch queue for 2023-11-07:

This queue, the last one before the 8.2 feature freeze, has miscellanous
changes that

Merge tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu into staging

ppc patch queue for 2023-11-07:

This queue, the last one before the 8.2 feature freeze, has miscellanous
changes that includes new PowerNV features and the new AmigaONE XE
board.

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# gpg: Signature made Wed 08 Nov 2023 04:46:49 HKT
# gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg: issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164

* tag 'pull-ppc-20231107' of https://gitlab.com/danielhb/qemu:
ppc: qtest already exports qtest_rtas_call()
hw/pci-host: Update PHB5 XSCOM registers
ppc/pnv: Fix number of I2C engines and ports for power9/10
ppc/pnv: Connect PNV I2C controller to powernv10
ppc/pnv: Connect I2C controller model to powernv9 chip
ppc/pnv: Add an I2C controller model
tests/avocado: Add test for amigaone board
hw/ppc: Add emulation of AmigaOne XE board
hw/pci-host: Add emulation of Mai Logic Articia S

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

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# 263b81ee 16-Oct-2023 Cédric Le Goater <clg@kaod.org>

ppc/pnv: Add an I2C controller model

The more recent IBM power processors have an embedded I2C
controller that is accessible by software via the XSCOM
address space.

Each instance of the I2C contro

ppc/pnv: Add an I2C controller model

The more recent IBM power processors have an embedded I2C
controller that is accessible by software via the XSCOM
address space.

Each instance of the I2C controller is capable of controlling
multiple I2C buses (one at a time). Prior to beginning a
transaction on an I2C bus, the bus must be selected by writing
the port number associated with the bus into the PORT_NUM
field of the MODE register. Once an I2C bus is selected,
the status of the bus can be determined by reading the
Status and Extended Status registers.

I2C bus transactions can be started by writing a command to
the Command register and reading/writing data from/to the
FIFO register.

Not supported :

. 10 bit I2C addresses
. Multimaster
. Slave

Signed-off-by: Cédric Le Goater <clg@kaod.org>
[milesg: Split wiring to powernv9 into its own commit]
[milesg: Added more detail to commit message]
[milesg: Added SPDX Licensed Identifier to new files]
[milesg: updated copyright dates]
[milesg: Added use of g_autofree]
[milesg: Added NULL check after pnv_i2c_get_bus]
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID: <20231016222013.3739530-2-milesg@linux.vnet.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>

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