Revision tags: v9.2.0, v9.1.2, v9.1.1 |
|
#
a53b9316 |
| 25-Sep-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
trivial patches for 2024-09-20
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEZKoqtTHVaQM2a/75gqpKJDselHgFAmbtJJU
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
trivial patches for 2024-09-20
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEZKoqtTHVaQM2a/75gqpKJDselHgFAmbtJJUACgkQgqpKJDse # lHjduhAAoZSS5+n2f8C4w4oboH9e5JSa6UAuVqGgju10SHm+VNgg2rQeeTD+J8uU # vXL5lZKIb/jPNfHmsS5Q8CsuzV0M+A0wCcZJHaK5clVc1pZWMqwPPT4g4BUyjURi # ptvQXWtTM049DDWZZXo+AHPQtko7f58EThn9fLBo/1yJe2UlBwhZwahKm3h66kkb # aO9TI9UVt06DmXAvPBK9IfgFjYzkUJRQnLLmJDXiLx6YbuixX+J2PjKav5NtacRE # KUArkLNfB00ouFYDOoLAnn/l+VWKIYkREeKbfQIj95BoejqAKsDztq35+oiRQbCZ # CznKgXMIBNJCCYvKJXAoZeslE3n7Q0dlJ3RppClBjzHOiZTM46yeTofzzFot7SCN # ERuV1WcTo53ooDvpvlP9S3d3P2i62eL5JPXgpN57Zuy7PTYQkcDq5wMTWlvm/OBy # /hzcmIm1KHrprjf/+aNRdeCT27Rf1YD8EiTaabgtTZA4r00DrTpopAJs8ncKfbrA # nxa8e7lNorx/PcBSJJA5iB1Q05y19eoLJcrCFMieFuG2s/oubm+bXrAuNjsSuJbS # Lq50dIO6UIJSrV59w0CTBDrOuVXUv8/jbqRCUBMEzbXfz8mW9e8PXL+evVa8rKfk # 6EMmDqC0/CmRrHT5uKkqTLtxcYGagdww3WIUB88UgARxydRPhu8= # =++OB # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Sep 2024 08:30:29 BST # gpg: using RSA key 64AA2AB531D56903366BFEF982AA4A243B1E9478 # gpg: Good signature from "Michael Tokarev <mjt@debian.org>" [full] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full] # gpg: aka "Michael Tokarev <mjt@tls.msk.ru>" [full] # Primary key fingerprint: 9D8B E14E 3F2A 9DD7 9199 28F1 61AD 3D98 ECDF 2C8E # Subkey fingerprint: 64AA 2AB5 31D5 6903 366B FEF9 82AA 4A24 3B1E 9478
* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (22 commits) license: Update deprecated SPDX tag GPL-2.0 to GPL-2.0-only license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later license: Update deprecated SPDX tag LGPL-2.0+ to LGPL-2.0-or-later license: Simplify GPL-2.0-or-later license descriptions tests/functional: Correct typo in test_netdev_ethtool.py SPDX tag tests/bench: Rename test_akcipher_keys.inc -> test_akcipher_keys.c.inc target/hexagon: Rename macros.inc -> macros.h.inc tests/functional: Put the or1k_sim test into the slow category tests/qemu-iotests/testenv: Use the "r2d" machine for sh4/sh4eb tests/qemu-iotests/testenv: Use the "virt" machine for or1k util/cutils: Remove unused qemu_get_exec_dir hw/sysbus: Remove unused sysbus_mmio_unmap envlist: Remove unused envlist_parse hw/display: Fix mirrored output in dm163 hw/virtio/Kconfig: Include vhost-user-scmi only on arm targets tests/unit: Really build pbkdf test on macOS hw/loongarch/virt: Add description for virt machine type hw/mips/jazz: fix typo in in-built NIC alias ppc: fix incorrect spelling of PowerMac linux-user/syscall.c: eliminate other explicit LFS usages ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
97d348cc |
| 11-Sep-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later
The 'GPL-2.0+' license identifier has been deprecated since license list version 2.0rc2 [1] and replaced by the 'GPL-2.0-or-later' [2
license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later
The 'GPL-2.0+' license identifier has been deprecated since license list version 2.0rc2 [1] and replaced by the 'GPL-2.0-or-later' [2] tag.
[1] https://spdx.org/licenses/GPL-2.0+.html [2] https://spdx.org/licenses/GPL-2.0-or-later.html
Mechanical patch running:
$ sed -i -e s/GPL-2.0+/GPL-2.0-or-later/ \ $(git grep -lP 'SPDX-License-Identifier: \W+GPL-2.0\+[ $]' \ | egrep -v '^linux-headers|^include/standard-headers')
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
show more ...
|
Revision tags: v9.1.0 |
|
#
14639717 |
| 31-Jan-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
trivial patches for 2024-01-31
# -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmW6NSc
Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging
trivial patches for 2024-01-31
# -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmW6NScPHG1qdEB0bHMu # bXNrLnJ1AAoJEHAbT2saaT5ZdQYH/2fhfhZotH0V2qAcMxlOoHbAE9UhZNRsSYtf # QFP0GXFYFAMm7LHkPUbvKgO7LylKWAOMn/zKZqgj1Vf1EpoKQ2FwLtR/buDz86Ec # pi2OrDPRA7Ay5c3ow3YZZkUOhQTTcR5rNjYctPtt/J4j8ol/z5vre7weJIg2bCJe # zI7vIVg7iFFzbkXY20KHngJ5nDC+aEm7WaGlxAP8kfkvy324Wy9O2k8qu2J5zbLT # HGvh3rwEDvRTYe4CaKFFHWNV0m4092HAr/dJBobugI5VZ6QQpK6Tgy8N+4ZrCHD2 # SjUKeym85VTOYGuY8b18fk5MQK2SzsfBUJ4x8VGC75W4mJ8agdc= # =HImO # -----END PGP SIGNATURE----- # gpg: Signature made Wed 31 Jan 2024 11:55:19 GMT # gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59 # gpg: issuer "mjt@tls.msk.ru" # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full] # gpg: aka "Michael Tokarev <mjt@debian.org>" [full] # Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D 4324 457C E0A0 8044 65C5 # Subkey fingerprint: 7B73 BAD6 8BE7 A2C2 8931 4B22 701B 4F6B 1A69 3E59
* tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: (21 commits) hw/hyperv: Include missing headers hw/intc/xics: Include missing 'cpu.h' header hw/arm: Add `\n` to hint message hw/loongarch: Add `\n` to hint message hw/i386: Add `\n` to hint message backends/hostmem: Fix block comments style (checkpatch.pl warnings) misc: Clean up includes riscv: Clean up includes cxl: Clean up includes include: Clean up includes m68k: Clean up includes acpi: Clean up includes aspeed: Clean up includes disas/riscv: Clean up includes hyperv: Clean up includes scripts/clean-includes: Update exclude list mailmap: Fix Stefan Weil email qemu-docs: Update options for graphical frontends qapi/migration.json: Fix the member name for MigrationCapability colo: examples: remove mentions of script= and (wrong) downscript= ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
ee88df50 |
| 25-Jan-2024 |
Peter Maydell <peter.maydell@linaro.org> |
acpi: Clean up includes
This commit was created with scripts/clean-includes: ./scripts/clean-includes --git acpi include/hw/*/*acpi.h hw/*/*acpi.c
All .c should include qemu/osdep.h first. The sc
acpi: Clean up includes
This commit was created with scripts/clean-includes: ./scripts/clean-includes --git acpi include/hw/*/*acpi.h hw/*/*acpi.c
All .c should include qemu/osdep.h first. The script performs three related cleanups:
* Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
show more ...
|
#
34eac35f |
| 10-Jan-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging
RISC-V PR for 9.0
* Make vector whole-register move (vmv) depend on vtype register * Fix th.dcache.cval1
Merge tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu into staging
RISC-V PR for 9.0
* Make vector whole-register move (vmv) depend on vtype register * Fix th.dcache.cval1 priviledge check * Don't allow write mstatus_vs without RVV * Use hwaddr instead of target_ulong for RV32 * Fix machine IDs QOM getters\ * Fix KVM reg id sizes * ACPI: Enable AIA, PLIC and update RHCT * Fix the interrupts-extended property format of PLIC * Add support for Zacas extension * Add amocas.[w,d,q] instructions * Document acpi parameter of virt machine * RVA22 profiles support * Remove group setting of KVM AIA if the machine only has 1 socket * Add RVV CSRs to KVM * sifive_u: Update S-mode U-Boot image build instructions * Upgrade OpenSBI from v1.3.1 to v1.4 * pmp: Ignore writes when RW=01 and MML=0 * Assert that the CSR numbers will be correct * Don't adjust vscause for exceptions * Ensure mideleg is set correctly on reset
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmWeW8kACgkQr3yVEwxT # gBMB3BAAtpb7dC/NqDOjo/LjGf81wYUnF0KcfJUIbuHEM9S03mKJEvngV/sUhg+A # fzsoJazijQZk2+Y02WLT/o+ppRDegb4P6n54Nn13xr024Dn2jf45+EKDLI+vtU5y # lhwp/LH3SEo2MM/Qr0njl8+jJ7W9adhZeK6x+NFaLaQJ291xupbcwEnScdv2bPAo # gvbM6yrfUoZ25MsQKIDGssozdGRwOD/keAT0q8C0gKDamqXBDrI80BOVhRms+uLm # R33DXsAegPKluJTa9gfaWFI0eK34WHXRvSIjE36nZlGNNgqLAVdM2/QozMVz4cKA # Ymz1nzqB9HeSn1pM4KCK/Y3LH89qLGWtyHYgldiDXA/wSyKajwkbXSWFOT9gPDqV # i+5BRDvU0zIeMIt+ROqNKgx1Hry6U2aycMNsdHTmygJbGEpiTaXuES5tt+LKsyHe # w/7a6wPd/kh9LQhXYQ4qbn7L534tWvn8zWyvKLZLxmYPcOn6SdjFbKWmk5ARky2W # sx9ojn9ANlYaLfzQ3TMRcIhWD6n8Si3KFNiQ3353E8xkRkyfu0WHyXAy8/kIc5UT # nScO2YD68XkdkcLF6uLUKuGiVZXFWXRY1Ttz9tvEmBckVsg6TIkoMONHeUWNP7ly # A0bJwN5qEOk6XIYKHWwX5UzvkcfUpOb5VmuLuv3gRoNX0A7/+fc= # =5K9J # -----END PGP SIGNATURE----- # gpg: Signature made Wed 10 Jan 2024 08:56:41 GMT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20240110' of https://github.com/alistair23/qemu: (65 commits) target/riscv: Ensure mideleg is set correctly on reset target/riscv: Don't adjust vscause for exceptions target/riscv: Assert that the CSR numbers will be correct target/riscv: pmp: Ignore writes when RW=01 and MML=0 roms/opensbi: Upgrade from v1.3.1 to v1.4 docs/system/riscv: sifive_u: Update S-mode U-Boot image build instructions target/riscv/kvm: add RVV and Vector CSR regs target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize() linux-headers: riscv: add ptrace.h linux-headers: Update to Linux v6.7-rc5 target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1 socket target/riscv: add rva22s64 cpu target/riscv: add RVA22S64 profile target/riscv: add 'parent' in profile description target/riscv: add satp_mode profile support target/riscv/cpu.c: add riscv_cpu_is_32bit() target/riscv/cpu.c: finalize satp_mode earlier target/riscv: add priv ver restriction to profiles target/riscv: implement svade target/riscv: add 'rva22u64' CPU ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
4c7f4f4f |
| 18-Dec-2023 |
Sunil V L <sunilvl@ventanamicro.com> |
hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location
RISC-V also needs to use the same code to create fw_cfg in DSDT. So, avoid code duplication by moving the code in arm and riscv t
hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location
RISC-V also needs to use the same code to create fw_cfg in DSDT. So, avoid code duplication by moving the code in arm and riscv to a device specific file.
Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20231218150247.466427-2-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|