Merge tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20230106

# gpg: Signature made Fri 06 Jan 2023 06:21:22 GMT
# gpg: using RSA key B8

Merge tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu into staging

pull-loongarch-20230106

# gpg: Signature made Fri 06 Jan 2023 06:21:22 GMT
# gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF

* tag 'pull-loongarch-20230106' of https://gitlab.com/gaosong/qemu:
hw/intc/loongarch_pch: Change default irq number of pch irq controller
hw/intc/loongarch_pch_pic: add irq number property
hw/intc/loongarch_pch_msi: add irq number property

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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hw/intc/loongarch_pch_msi: add irq number property

This patch adds irq number property for loongarch msi interrupt
controller, and remove hard coding irq number macro.

Signed-off-by: Tianrui Zhao <

hw/intc/loongarch_pch_msi: add irq number property

This patch adds irq number property for loongarch msi interrupt
controller, and remove hard coding irq number macro.

Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230104020518.2564263-2-zhaotianrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>

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Merge tag 'pull-la-20220704' of https://gitlab.com/rth7680/qemu into staging

LoongArch patch queue:
Support linux-user.
Fixes for CSR BADV.
Fix ASRT{LE,GT} exception.
Fixes for LS7A RTC.
F

Merge tag 'pull-la-20220704' of https://gitlab.com/rth7680/qemu into staging

LoongArch patch queue:
Support linux-user.
Fixes for CSR BADV.
Fix ASRT{LE,GT} exception.
Fixes for LS7A RTC.
Fix for interrupt vector spacing.

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# gpg: Signature made Mon 04 Jul 2022 03:01:52 PM +0530
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-la-20220704' of https://gitlab.com/rth7680/qemu: (23 commits)
target/loongarch: Add lock when writing timer clear reg
target/loongarch: Fix the meaning of ECFG reg's VS field
hw/rtc/ls7a_rtc: Fix 'calculate' spelling errors
hw/rtc/ls7a_rtc: Use tm struct pointer as arguments in toy_time_to_val()
hw/rtc/ls7a_rtc: Fix rtc enable and disable function
hw/rtc/ls7a_rtc: Add reset function
hw/rtc/ls7a_rtc: Remove unimplemented device in realized function
hw/rtc/ls7a_rtc: Fix timer call back function
hw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch writing function
hw/intc/loongarch_pch_msi: Fix msi vector convertion
target/loongarch: Update README
default-configs: Add loongarch linux-user support
target/loongarch: Adjust functions and structure to support user-mode
target/loongarch: remove unused include hw/loader.h
target/loongarch: Fix helper_asrtle_d/asrtgt_d raise wrong exception
target/loongarch: Fix missing update CSR_BADV
target/loongarch: remove badaddr from CPULoongArch
scripts: add loongarch64 binfmt config
linux-user: Add LoongArch cpu_loop support
linux-user: Add LoongArch syscall support
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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hw/intc/loongarch_pch_msi: Fix msi vector convertion

Loongarch pch msi intc connects to extioi controller, the range of irq
number is 64-255. Add a property for irqbase, so that we can compute
the

hw/intc/loongarch_pch_msi: Fix msi vector convertion

Loongarch pch msi intc connects to extioi controller, the range of irq
number is 64-255. Add a property for irqbase, so that we can compute
the irq offset from the view of pch_msi controller with the method:

msi vector (from view of upper extioi intc) - irqbase

Signed-off-by: Mao Bibo <maobibo@loongson.cn>
Message-Id: <20220701030740.2469162-1-maobibo@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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Merge tag 'pull-la-20220606' of https://gitlab.com/rth7680/qemu into staging

Initial LoongArch support.

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Merge tag 'pull-la-20220606' of https://gitlab.com/rth7680/qemu into staging

Initial LoongArch support.

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# gpg: Signature made Mon 06 Jun 2022 04:09:10 PM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-la-20220606' of https://gitlab.com/rth7680/qemu: (43 commits)
target/loongarch: 'make check-tcg' support
tests/tcg/loongarch64: Add hello/memory test in loongarch64 system
target/loongarch: Add gdb support.
hw/loongarch: Add LoongArch virt power manager support.
hw/loongarch: Add LoongArch load elf function.
hw/loongarch: Add LoongArch ls7a rtc device support
hw/loongarch: Add some devices support for 3A5000.
Enable common virtio pci support for LoongArch
hw/loongarch: Add irq hierarchy for the system
hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)
hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC)
hw/loongarch: Add LoongArch ipi interrupt support(IPI)
hw/loongarch: Add support loongson3 virt machine type.
target/loongarch: Add timer related instructions support.
target/loongarch: Add other core instructions support
target/loongarch: Add TLB instruction support
target/loongarch: Add LoongArch IOCSR instruction
target/loongarch: Add LoongArch CSR instruction
target/loongarch: Add constant timer support
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)

This patch realize PCH-MSI interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Ga

hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI)

This patch realize PCH-MSI interrupt controller.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220606124333.2060567-34-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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