Revision tags: v9.2.0, v9.1.2, v9.1.1 |
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#
e10cd938 |
| 26-Sep-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'mem-2024-09-24' of https://github.com/davidhildenbrand/qemu into staging
Hi,
"Host Memory Backends" and "Memory devices" queue ("mem"): - Kconfig fix for virtio-based memory devices - vi
Merge tag 'mem-2024-09-24' of https://github.com/davidhildenbrand/qemu into staging
Hi,
"Host Memory Backends" and "Memory devices" queue ("mem"): - Kconfig fix for virtio-based memory devices - virtio-mem support for suspend+wake-up with plugged memory - hostmem fix when specifying "merge=off"
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* tag 'mem-2024-09-24' of https://github.com/davidhildenbrand/qemu: hostmem: Apply merge property after the memory region is initialized virtio-mem: Add support for suspend+wake-up with plugged memory virtio-mem: Use new Resettable framework instead of LegacyReset reset: Add RESET_TYPE_WAKEUP reset: Use ResetType for qemu_devices_reset() and MachineClass::reset() virtio: kconfig: memory devices are PCI only
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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1b063fe2 |
| 04-Sep-2024 |
Juraj Marcin <jmarcin@redhat.com> |
reset: Use ResetType for qemu_devices_reset() and MachineClass::reset()
Currently, both qemu_devices_reset() and MachineClass::reset() use ShutdownCause for the reason of the reset. However, the Res
reset: Use ResetType for qemu_devices_reset() and MachineClass::reset()
Currently, both qemu_devices_reset() and MachineClass::reset() use ShutdownCause for the reason of the reset. However, the Resettable interface uses ResetState, so ShutdownCause needs to be translated to ResetType somewhere. Translating it qemu_devices_reset() makes adding new reset types harder, as they cannot always be matched to a single ShutdownCause here, and devices may need to check the ResetType to determine what to reset and if to reset at all.
This patch moves this translation up in the call stack to qemu_system_reset() and updates all MachineClass children to use the ResetType instead.
Message-ID: <20240904103722.946194-2-jmarcin@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Juraj Marcin <jmarcin@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
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Revision tags: v9.1.0 |
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#
83baec64 |
| 25-Apr-2024 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Implement FEAT_NMI and NMI support in the GICv3 * hw/dma: avoid apparent ov
Merge tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Implement FEAT_NMI and NMI support in the GICv3 * hw/dma: avoid apparent overflow in soc_dma_set_request * linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code * Add ResetType argument to Resettable hold and exit phase methods * Add RESET_TYPE_SNAPSHOT_LOAD ResetType * Implement STM32L4x5 USART
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* tag 'pull-target-arm-20240425' of https://git.linaro.org/people/pmaydell/qemu-arm: (37 commits) tests/qtest: Add tests for the STM32L4x5 USART hw/arm: Add the USART to the stm32l4x5 SoC hw/char/stm32l4x5_usart: Add options for serial parameters setting hw/char/stm32l4x5_usart: Enable serial read and write hw/char: Implement STM32L4x5 USART skeleton reset: Add RESET_TYPE_SNAPSHOT_LOAD docs/devel/reset: Update to new API for hold and exit phase methods hw, target: Add ResetType argument to hold and exit phase methods scripts/coccinelle: New script to add ResetType to hold and exit phases allwinner-i2c, adm1272: Use device_cold_reset() for software-triggered reset hw/misc: Don't special case RESET_TYPE_COLD in npcm7xx_clk, gcr linux-user/flatload.c: Remove unused bFLT shared-library and ZFLAT code hw/dma: avoid apparent overflow in soc_dma_set_request hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMI target/arm: Add FEAT_NMI to max hw/intc/arm_gicv3: Report the VINMI interrupt hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() hw/intc/arm_gicv3: Implement NMI interrupt priority hw/intc/arm_gicv3: Handle icv_nmiar1_read() for icc_nmiar1_read() hw/intc/arm_gicv3: Add NMI handling CPU interface registers ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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631f46d4 |
| 12-Apr-2024 |
Peter Maydell <peter.maydell@linaro.org> |
reset: Add RESET_TYPE_SNAPSHOT_LOAD
Some devices and machines need to handle the reset before a vmsave snapshot is loaded differently -- the main user is the handling of RNG seed information, which
reset: Add RESET_TYPE_SNAPSHOT_LOAD
Some devices and machines need to handle the reset before a vmsave snapshot is loaded differently -- the main user is the handling of RNG seed information, which does not want to put a new RNG seed into a ROM blob when we are doing a snapshot load.
Currently this kind of reset handling is supported only for: * TYPE_MACHINE reset methods, which take a ShutdownCause argument * reset functions registered with qemu_register_reset_nosnapshotload
To allow a three-phase-reset device to also distinguish "snapshot load" reset from the normal kind, add a new ResetType RESET_TYPE_SNAPSHOT_LOAD. All our existing reset methods ignore the reset type, so we don't need to update any device code.
Add the enum type, and make qemu_devices_reset() use the right reset type for the ShutdownCause it is passed. This allows us to get rid of the device_reset_reason global we were using to implement qemu_register_reset_nosnapshotload().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20240412160809.1260625-7-peter.maydell@linaro.org
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ad80e367 |
| 12-Apr-2024 |
Peter Maydell <peter.maydell@linaro.org> |
hw, target: Add ResetType argument to hold and exit phase methods
We pass a ResetType argument to the Resettable class enter phase method, but we don't pass it to hold and exit, even though the call
hw, target: Add ResetType argument to hold and exit phase methods
We pass a ResetType argument to the Resettable class enter phase method, but we don't pass it to hold and exit, even though the callsites have it readily available. This means that if a device cared about the ResetType it would need to record it in the enter phase method to use later on. Pass the type to all three of the phase methods to avoid having to do that.
Commit created with
for dir in hw target include; do \ spatch --macro-file scripts/cocci-macro-file.h \ --sp-file scripts/coccinelle/reset-type.cocci \ --keep-comments --smpl-spacing --in-place \ --include-headers --dir $dir; done
and no manual edits.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org
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158a054c |
| 27-Feb-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-target-arm-20240227-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Handle atomic updates of page tables entries in MMIO during PTW * Adverti
Merge tag 'pull-target-arm-20240227-1' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Handle atomic updates of page tables entries in MMIO during PTW * Advertise Cortex-A53 erratum #843419 fix via REVIDR * MAINTAINERS: Cover hw/ide/ahci-allwinner.c with AllWinner A10 machine * misc: m48t59: replace qemu_system_reset_request() call with watchdog_perform_action() * misc: pxa2xx_timer: replace qemu_system_reset_request() call with watchdog_perform_action() * xlnx-versal-ospi: disable reentrancy detection for iomem_dac * sbsa-ref: Simplify init since PCIe is always enabled * stm32l4x5: Use TYPE_OR_IRQ when connecting STM32L4x5 EXTI fan-in IRQs * pl031: Update last RTCLR value on write in case it's read back * block: m25p80: Add support of mt35xu02gbba * xlnx-versal-virt: Add machine property ospi-flash * reset: refactor system reset to be three-phase aware * new board model raspi4b
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* tag 'pull-target-arm-20240227-1' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits) docs/system/arm: Add RPi4B to raspi.rst hw/misc/bcm2835_property: Add missed BCM2835 properties tests/avocado/boot_linux_console.py: Add Rpi4b boot tests hw/arm/bcm2838_peripherals: Add clock_isp stub hw/arm: Add memory region for BCM2837 RPiVid ASB hw/arm/raspi4b: Temporarily disable unimplemented rpi4b devices hw/arm: Introduce Raspberry PI 4 machine hw/arm: Add GPIO and SD to BCM2838 periph hw/gpio: Connect SD controller to BCM2838 GPIO hw/gpio: Implement BCM2838 GPIO functionality hw/gpio: Add BCM2838 GPIO stub hw/arm/bcm2838: Add GIC-400 to BCM2838 SoC hw/arm: Introduce BCM2838 SoC hw/arm/raspi: Split out raspi machine common part hw/arm/bcm2853_peripherals: Split out common part of peripherals hw/arm/bcm2836: Split out common part of BCM283X classes docs/devel/reset: Update to discuss system reset hw/core/machine: Use qemu_register_resettable for sysbus reset hw/core/reset: Implement qemu_register_reset via qemu_register_resettable hw/core/reset: Add qemu_{register, unregister}_resettable() ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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71b3ea37 |
| 20-Feb-2024 |
Peter Maydell <peter.maydell@linaro.org> |
hw/core/reset: Implement qemu_register_reset via qemu_register_resettable
Reimplement qemu_register_reset() via qemu_register_resettable().
We define a new LegacyReset object which implements Reset
hw/core/reset: Implement qemu_register_reset via qemu_register_resettable
Reimplement qemu_register_reset() via qemu_register_resettable().
We define a new LegacyReset object which implements Resettable and defines its reset hold phase method to call a QEMUResetHandler function. When qemu_register_reset() is called, we create a new LegacyReset object and add it to the simulation_reset ResettableContainer. When qemu_unregister_reset() is called, we find the LegacyReset object in the container and remove it.
This implementation of qemu_unregister_reset() means we'll end up scanning the ResetContainer's list of child objects twice, once to find the LegacyReset object, and once in g_ptr_array_remove(). In theory we could avoid this by having the ResettableContainer interface include a resettable_container_remove_with_equal_func() that took a callback method so that we could use g_ptr_array_find_with_equal_func() and g_ptr_array_remove_index(). But we don't expect qemu_unregister_reset() to be called frequently or in hot paths, and we expect the simulation_reset container to usually not have many children.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20240220160622.114437-9-peter.maydell@linaro.org Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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86fae16e |
| 20-Feb-2024 |
Peter Maydell <peter.maydell@linaro.org> |
hw/core/reset: Add qemu_{register, unregister}_resettable()
Implement new functions qemu_register_resettable() and qemu_unregister_resettable(). These are intended to be three-phase-reset aware equ
hw/core/reset: Add qemu_{register, unregister}_resettable()
Implement new functions qemu_register_resettable() and qemu_unregister_resettable(). These are intended to be three-phase-reset aware equivalents of the old qemu_register_reset() and qemu_unregister_reset(). Instead of passing in a function pointer and opaque, you register any QOM object that implements the Resettable interface.
The implementation is simple: we have a single global instance of a ResettableContainer, which we reset in qemu_devices_reset(), and the Resettable objects passed to qemu_register_resettable() are added to it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20240220160622.114437-8-peter.maydell@linaro.org Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
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Revision tags: v8.0.0, v7.2.0 |
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d0d8d570 |
| 27-Oct-2022 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-target-arm-20221027' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Implement FEAT_E0PD * Implement FEAT_HAFDBS * honor HCR_E2H and HCR_TGE in
Merge tag 'pull-target-arm-20221027' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * Implement FEAT_E0PD * Implement FEAT_HAFDBS * honor HCR_E2H and HCR_TGE in arm_excp_unmasked() * hw/arm/virt: Fix devicetree warnings about the virtio-iommu node * hw/core/resettable: fix reset level counting * hw/hyperv/hyperv.c: Use device_cold_reset() instead of device_legacy_reset() * imx: reload cmp timer outside of the reload ptimer transaction * x86: do not re-randomize RNG seed on snapshot load * m68k/virt: do not re-randomize RNG seed on snapshot load * m68k/q800: do not re-randomize RNG seed on snapshot load * arm: re-randomize rng-seed on reboot * riscv: re-randomize rng-seed on reboot * mips/boston: re-randomize rng-seed on reboot * openrisc: re-randomize rng-seed on reboot * rx: re-randomize rng-seed on reboot
# -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmNagAQZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3sv6D/0VXf61t6IcmQ342L5IeUeA # jixouWQhma3WwFDjbEo3BehgBhdwH2gxF8XWZNudV1x5P4JbCwiD/sm9FKtNY3IX # lOpcg4F7Ge6EHCEQ5PM75G4TNQBw1BTwGuNrXm8kpVZ7i7C4Zo3gzbqVYv59d406 # fMwZBZwwavn9xYI/ZOUq3CKv2W/xrveFIEfafQB1mmcu4azZRLlOdMXvsMY/Te1/ # GQ+0RPcemNfvfFwYfMKT9dqiCWgqzAoiGQNH2944mTnoJJMsI0JLcXP2z/4fFfYv # J1m7mhOO9KiqUWzxJofQOgQIic1q6AY0lLw272mA/rbwwlmlm/bNl1DGE5Lyw64d # t/dDWE6X8IHPqPzqqrOd8vpKIKUriDSL83D5uULpPXaQwyckTFDsAMu5VX4uswbm # B+SizTghSNwMbOq1XsQg6DDiHEelbwwrltsLOSQujXrrngtSxjWXuFgWem4gT8HL # uVQtrfrASV/gNBLRNX73vuL6pJaTEVqk53JI8MamZEIRLO1s6/nreOR13E+0611T # iMywoOhAQA3RDe9NU0zgg6EGyskRZQG1CRTDQAz1sAt8WcHokg7Yj7LlfGE+/+Bh # 4cIuJI56Uf3DJF51A52+roaQkZDJZZkfE1EG8uMDIWszP5v2GDcwx3AS3FLuaDfH # QHPsecbzEURFTmdt5VrKzg== # =RD6C # -----END PGP SIGNATURE----- # gpg: Signature made Thu 27 Oct 2022 08:56:36 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20221027' of https://git.linaro.org/people/pmaydell/qemu-arm: (31 commits) mips/malta: pass RNG seed via env var and re-randomize on reboot rx: re-randomize rng-seed on reboot openrisc: re-randomize rng-seed on reboot mips/boston: re-randomize rng-seed on reboot m68k/q800: do not re-randomize RNG seed on snapshot load m68k/virt: do not re-randomize RNG seed on snapshot load riscv: re-randomize rng-seed on reboot arm: re-randomize rng-seed on reboot x86: do not re-randomize RNG seed on snapshot load device-tree: add re-randomization helper function reset: allow registering handlers that aren't called by snapshot loading target/arm: Use the max page size in a 2-stage ptw target/arm: Implement FEAT_HAFDBS, dirty bit portion target/arm: Implement FEAT_HAFDBS, access flag portion target/arm: Tidy merging of attributes from descriptor and table target/arm: Consider GP an attribute in get_phys_addr_lpae target/arm: Don't shift attrs in get_phys_addr_lpae target/arm: Fix fault reporting in get_phys_addr_lpae target/arm: Remove loop from get_phys_addr_lpae target/arm: Add ARMFault_UnsuppAtomicUpdate ...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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7966d70f |
| 24-Oct-2022 |
Jason A. Donenfeld <Jason@zx2c4.com> |
reset: allow registering handlers that aren't called by snapshot loading
Snapshot loading only expects to call deterministic handlers, not non-deterministic ones. So introduce a way of registering h
reset: allow registering handlers that aren't called by snapshot loading
Snapshot loading only expects to call deterministic handlers, not non-deterministic ones. So introduce a way of registering handlers that won't be called when reseting for snapshots.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Message-id: 20221025004327.568476-2-Jason@zx2c4.com [PMM: updated json doc comment with Markus' text; fixed checkpatch style nit] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v7.0.0 |
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#
33072497 |
| 21-Mar-2022 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-misc-2022-03-21' of git://repo.or.cz/qemu/armbru into staging
Miscellaneous patches patches for 2022-03-21
# gpg: Signature made Mon 21 Mar 2022 14:48:16 GMT # gpg: u
Merge tag 'pull-misc-2022-03-21' of git://repo.or.cz/qemu/armbru into staging
Miscellaneous patches patches for 2022-03-21
# gpg: Signature made Mon 21 Mar 2022 14:48:16 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* tag 'pull-misc-2022-03-21' of git://repo.or.cz/qemu/armbru: Use g_new() & friends where that makes obvious sense 9pfs: Use g_new() & friends where that makes obvious sense scripts/coccinelle: New use-g_new-etc.cocci block-qdict: Fix -Werror=maybe-uninitialized build failure
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
b21e2380 |
| 15-Mar-2022 |
Markus Armbruster <armbru@redhat.com> |
Use g_new() & friends where that makes obvious sense
g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer, for two reasons. One, it catches multiplication overflowing size_t. Two, i
Use g_new() & friends where that makes obvious sense
g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer, for two reasons. One, it catches multiplication overflowing size_t. Two, it returns T * rather than void *, which lets the compiler catch more type errors.
This commit only touches allocations with size arguments of the form sizeof(T).
Patch created mechanically with:
$ spatch --in-place --sp-file scripts/coccinelle/use-g_new-etc.cocci \ --macro-file scripts/cocci-macro-file.h FILES...
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20220315144156.1595462-4-armbru@redhat.com> Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
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Revision tags: v6.2.0, v6.1.0, v5.2.0, v5.0.0, v4.2.0, v4.0.0, v4.0.0-rc1, v4.0.0-rc0 |
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#
15bede55 |
| 11-Jan-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* HAX support for Linux hosts (Alejandro) * esp bugfixes (Guenter) * Windows build cleanup (Marc-André) * checkpatch log
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* HAX support for Linux hosts (Alejandro) * esp bugfixes (Guenter) * Windows build cleanup (Marc-André) * checkpatch logic improvements (Paolo) * coalesced range bugfix (Paolo) * switch testsuite to TAP (Paolo) * QTAILQ rewrite (Paolo) * block/iscsi.c cancellation fixes (Stefan) * improve selection of the default accelerator (Thomas)
# gpg: Signature made Fri 11 Jan 2019 14:47:40 GMT # gpg: using RSA key BFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini/tags/for-upstream: (34 commits) avoid TABs in files that only contain a few remove space-tab sequences scripts: add script to convert multiline comments into 4-line format hw/watchdog/wdt_i6300esb: remove a unnecessary comment checkpatch: warn about qemu/queue.h head structs that are not typedef-ed qemu/queue.h: simplify reverse access to QTAILQ qemu/queue.h: reimplement QTAILQ without pointer-to-pointers qemu/queue.h: remove Q_TAILQ_{HEAD,ENTRY} qemu/queue.h: typedef QTAILQ heads qemu/queue.h: leave head structs anonymous unless necessary vfio: make vfio_address_spaces static qemu/queue.h: do not access tqe_prev directly test: replace gtester with a TAP driver test: execute g_test_run when tests are skipped qga: drop < Vista compatibility build-sys: build with Vista API by default build-sys: move windows defines in osdep.h header build-sys: don't include windows.h, osdep.h does it scsi: esp: Defer command completion until previous interrupts have been handled esp-pci: Fix status register write erase control ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v3.1.0, v3.1.0-rc5 |
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#
b58deb34 |
| 06-Dec-2018 |
Paolo Bonzini <pbonzini@redhat.com> |
qemu/queue.h: leave head structs anonymous unless necessary
Most list head structs need not be given a name. In most cases the name is given just in case one is going to use QTAILQ_LAST, QTAILQ_PRE
qemu/queue.h: leave head structs anonymous unless necessary
Most list head structs need not be given a name. In most cases the name is given just in case one is going to use QTAILQ_LAST, QTAILQ_PREV or reverse iteration, but this does not apply to lists of other kinds, and even for QTAILQ in practice this is only rarely needed. In addition, we will soon reimplement those macros completely so that they do not need a name for the head struct. So clean up everything, not giving a name except in the rare case where it is necessary.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v3.1.0-rc4, v3.1.0-rc3, v3.1.0-rc2, v3.1.0-rc1, v3.1.0-rc0, libfdt-20181002, ppc-for-3.1-20180925, ppc-for-3.1-20180907, ppc-for-3.1-20180821, v3.0.0, v3.0.0-rc4, v2.12.1, ppc-for-3.0-20180801, v3.0.0-rc3, v3.0.0-rc2, v3.0.0-rc1, ppc-for-3.0-20180716, v3.0.0-rc0, ppc-for-3.0-20180709, ppc-for-3.0-20180703, v2.11.2, ppc-for-3.0-20180622, ppc-for-3.0-20180618, ppc-for-3.0-20180612, ppc-for-2.13-20180504, ppc-for-2.13-20180427, v2.12.0, v2.12.0-rc4, v2.12.0-rc3, ppc-for-2.12-20180410, v2.12.0-rc2, v2.12.0-rc1, v2.12.0-rc0, ppc-for-2.12-20180319, ppc-for-2.12-20180315, ppc-for-2.12-20180306, ppc-for-2.12-20180302, ppc-for-2.12-20180216, v2.11.1, ppc-for-2.12-20180212, ppc-for-2.12-20180129, ppc-for-2.12-20180121, ppc-for-2.12-20180119, ppc-for-2.12-20180117, ppc-for-2.12-20180111, ppc-for-2.12-20180108, ppc-for-2.12-20180103, ppc-for-2.12-20171219, v2.10.2, ppc-for-2.12-20171215, v2.11.0, v2.11.0-rc5, v2.11.0-rc4, ppc-for-2.11-20171205, ppc-for-2.11-20171204, v2.11.0-rc3, ppc-for-2.11-20171127, ppc-for-2.11-20171122, v2.11.0-rc2, ppc-for-2.11-20171120, v2.11.0-rc1, ppc-for-2.11-20171114, ppc-for-2.11-20171108, v2.11.0-rc0, ppc-for-2.11-20171017, v2.10.1, ppc-for-2.11-20170927, ppc-for-2.11-20170915, ppc-for-2.11-20170908, v2.9.1, v2.10.0, v2.10.0-rc4, ppc-for-2.10-20170823, ppc-for-2.10-20170822, v2.10.0-rc3, ppc-for-2.10-20170809, v2.10.0-rc2, v2.10.0-rc1, ppc-for-2.10-20170731, v2.10.0-rc0, ppc-for-2.10-20170725, ppc-for-2.10-20170717, ppc-for-2.10-20170714, ppc-for-2.10-20170711, ppc-for-2.10-20170630, ppc-for-2.10-20170609, ppc-for-2.10-20170606, ppc-for-2.10-20170525, ppc-for-2.10-20170511, ppc-for-2.10-20170510, ppc-for-2.10-20170426, ppc-for-2.10-20170424, v2.8.1.1, v2.9.0, v2.9.0-rc5, v2.9.0-rc4, v2.9.0-rc3, ppc-for-2.9-20170403, v2.8.1, ppc-for-2.9-20170329, v2.9.0-rc2, ppc-for-2.9-20170323, v2.9.0-rc1, v2.9.0-rc0, ppc-for-2.9-20170314, ppc-for-2.9-20170306, submodule-update-20170303, ppc-for-2.9-20170303, ppc-for-2.9-20170301, ppc-for-2.9-20170222, isa-cleanup-20170206, ppc-for-2.9-20170202 |
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#
598cf1c8 |
| 20-Jan-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* QOM interface fix (Eduardo) * RTC fixes (Gaohuai, Igor) * Memory leak fixes (Li Qiang, me) * Ctrl-a b regression (Marc
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
* QOM interface fix (Eduardo) * RTC fixes (Gaohuai, Igor) * Memory leak fixes (Li Qiang, me) * Ctrl-a b regression (Marc-André) * Stubs cleanups and fixes (Leif, me) * hxtool tweak (me) * HAX support (Vincent) * QemuThread, exec.c and SCSI fixes (Roman, Xinhua, me) * PC_COMPAT_2_8 fix (Marcelo) * stronger bitmap assertions (Peter)
# gpg: Signature made Fri 20 Jan 2017 12:49:01 GMT # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* remotes/bonzini/tags/for-upstream: (35 commits) pc.h: move x-mach-use-reliable-get-clock compat entry to PC_COMPAT_2_8 bitmap: assert that start and nr are non negative Revert "win32: don't run subprocess tests on Mingw32 platform" hax: add Darwin support Plumb the HAXM-based hardware acceleration support target/i386: Add Intel HAX files kvm: move cpu synchronization code KVM: PPC: eliminate unnecessary duplicate constants ramblock-notifier: new char: fix ctrl-a b not working exec: Add missing rcu_read_unlock x86: ioapic: fix fail migration when irqchip=split x86: ioapic: dump version for "info ioapic" x86: ioapic: add traces for ioapic hxtool: emit Texinfo headings as @subsection qemu-thread: fix qemu_thread_set_name() race in qemu_thread_create() serial: fix memory leak in serial exit scsi-block: fix direction of BYTCHK test for VERIFY commands pc: fix crash in rtc_set_memory() if initial cpu is marked as hotplugged acpi: filter based on CONFIG_ACPI_X86 rather than TARGET ...
# Conflicts: # include/hw/i386/pc.h
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Revision tags: ppc-for-2.9-20170112, master-20170112, v2.7.1, v2.8.0, v2.8.0-rc4, v2.8.0-rc3, ppc-for-2.8-20161201, v2.8.0-rc2, ppc-for-2.8-20161123, v2.8.0-rc1, isa-cleanup-20161118, qemu-kvm-1.5.3-127.el7, v2.8.0-rc0, ppc-for-2.8-20161115, qemu-kvm-1.5.3-126.el7_3.1, qemu-kvm-0.12.1.2-2.496.el6, ppc-for-2.8-20161028, qemu-kvm-0.12.1.2-2.495.el6, ppc-for-2.8-20161026 |
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#
2f7b92a0 |
| 24-Oct-2016 |
Paolo Bonzini <pbonzini@redhat.com> |
hw: move reset handlers from vl.c to hw/core
They are small, it is not worth stubbing them. Just include them in user-mode emulators and unit tests as well.
Signed-off-by: Paolo Bonzini <pbonzini@
hw: move reset handlers from vl.c to hw/core
They are small, it is not worth stubbing them. Just include them in user-mode emulators and unit tests as well.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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