Revision tags: v9.2.0, v9.1.2, v9.1.1, v9.1.0, v8.0.0, v7.2.0 |
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#
50eac424 |
| 17-Sep-2022 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-arm-20220914' of https://gitlab.com/rth7680/qemu into staging
Add cortex-a35. Fix bcm2835 framebuffer for rpi firmware. Add FEAT_ETS. Add FEAT_PMUv3p5. Cleanups to armv7m_load_kernel
Merge tag 'pull-arm-20220914' of https://gitlab.com/rth7680/qemu into staging
Add cortex-a35. Fix bcm2835 framebuffer for rpi firmware. Add FEAT_ETS. Add FEAT_PMUv3p5. Cleanups to armv7m_load_kernel.
# -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmMhwAsdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/7Xgf9Ezg+etwsEzY0EWtH # yoQ7ymJHM1VKqtLkbk9U+Ju18YHEi3fwbYbfLgzkAMFHKDUteKJivKm2w41tsw5g # lE+5PojQT3k8PffaqeFzKG/JsDPoqKtTa23WjkafbIQAbjRT8JtmF/JmSLaaxyqW # DozPXJ9jXMS+Q2BxHnoCBuy/Kb3zsqekCr8DOgUIXY5gcAB6q1I8SMX2BrhsIyvV # vZxNm+hFDCOJtXvkAekMrwGkiIBYoBNpswnv40ldeSvRtD8tnty73JUt+AnWoCwi # zH4k+CvWICIuZT7oxVecRhlOojtaP5cUTXs0+zhk6GxEx/X6wmXd42heO9ZJL0y1 # 6FH0xw== # =ohPU # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 Sep 2022 07:50:35 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-arm-20220914' of https://gitlab.com/rth7680/qemu: target/arm: Make boards pass base address to armv7m_load_kernel() target/arm: Remove useless TARGET_BIG_ENDIAN check in armv7m_load_kernel() target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max' target/arm: Support 64-bit event counters for FEAT_PMUv3p5 target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits target/arm: Rename pmu_8_n feature test functions target/arm: Detect overflow when calculating next PMU interrupt target/arm: Honour MDCR_EL2.HPMD in Secure EL2 target/arm: Ignore PMCR.D when PMCR.LC is set target/arm: Don't mishandle count when enabling or disabling PMU counters target/arm: Correct value returned by pmu_counter_mask() target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows target/arm: Add missing space in comment target/arm: Advertise FEAT_ETS for '-cpu max' target/arm: Implement ID_DFR1 target/arm: Implement ID_MMFR5 target/arm: Sort KVM reads of AArch32 ID registers into encoding order target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8 hw/arm/bcm2835_property: Add support for RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS target/arm: Add cortex-a35
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
761c532a |
| 23-Aug-2022 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make boards pass base address to armv7m_load_kernel()
Currently armv7m_load_kernel() takes the size of the block of memory where it should load the initial guest image, but assumes that
target/arm: Make boards pass base address to armv7m_load_kernel()
Currently armv7m_load_kernel() takes the size of the block of memory where it should load the initial guest image, but assumes that it should always load it at address 0. This happens to be true of all our M-profile boards at the moment, but it isn't guaranteed to always be so: M-profile CPUs can be configured (via init-svtor and init-nsvtor, which match equivalent hardware configuration signals) to have the initial vector table at any address, not just zero. (For instance the Teeny board has the boot ROM at address 0x0200_0000.)
Add a base address argument to armv7m_load_kernel(), so that callers now pass in both base address and size. All the current callers pass 0, so this is not a behaviour change.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220823160417.3858216-3-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.0.0, v6.2.0, v6.1.0 |
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#
99ae0cd9 |
| 03-Feb-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210203' into staging
target-arm queue: * hw/intc/arm_gic: Allow to use QTest without crashing * hw/char/exynos4210_uart: Fix b
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210203' into staging
target-arm queue: * hw/intc/arm_gic: Allow to use QTest without crashing * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled * hw/char/exynos4210_uart: Fix missing call to report ready for input * hw/arm/smmuv3: Fix addr_mask for range-based invalidation * hw/ssi/imx_spi: Fix various minor bugs * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register * hw/arm: Add missing Kconfig dependencies * hw/arm: Display CPU type in machine description
# gpg: Signature made Wed 03 Feb 2021 10:16:36 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210203: (21 commits) hw/arm: Display CPU type in machine description hw/net/can: ZynqMP CAN device requires PTIMER hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals hw/arm/xlnx-versal: Versal SoC requires ZDMA hw/arm/exynos4210: Add missing dependency on OR_IRQ hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register hw/ssi: imx_spi: Correct tx and rx fifo endianness hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Round up the burst length to be multiple of 8 hw/ssi: imx_spi: Disable chip selects when controller is disabled hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value hw/ssi: imx_spi: Remove pointless variable initialization hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/arm/smmuv3: Fix addr_mask for range-based invalidation hw/char/exynos4210_uart: Fix missing call to report ready for input hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
fd8f71b9 |
| 31-Jan-2021 |
Philippe Mathieu-Daudé <f4bug@amsat.org> |
hw/arm: Display CPU type in machine description
Most of ARM machines display their CPU when QEMU list the available machines (-M help). Some machines do not. Fix to unify the help output.
Signed-of
hw/arm: Display CPU type in machine description
Most of ARM machines display their CPU when QEMU list the available machines (-M help). Some machines do not. Fix to unify the help output.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210131184449.382425-7-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v5.2.0 |
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4dad0a9a |
| 21-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
QOM queue, 2020-09-18
Fixes: * Error value corrections (Markus Armbruster) * Correct object_class_dynamic
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
QOM queue, 2020-09-18
Fixes: * Error value corrections (Markus Armbruster) * Correct object_class_dynamic_cast_assert() documentation (Eduardo Habkost) * Ensure objects using QEMU_ALIGNED are properly aligned (Richard Henderson)
QOM cleanups (Eduardo Habkost): * Rename some constants * Simplify parameters of OBJECT_DECLARE* macros * Additional DECLARE_*CHECKER* usage * Additional OBJECT_DECLARE_TYPE usage * Additional OBJECT_DECLARE_SIMPLE_TYPE usage
# gpg: Signature made Fri 18 Sep 2020 21:45:29 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/machine-next-pull-request: Use OBJECT_DECLARE_SIMPLE_TYPE when possible Use OBJECT_DECLARE_TYPE when possible qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros qom: Remove ParentClassType argument from OBJECT_DECLARE_SIMPLE_TYPE scripts/codeconverter: Update to latest version target/s390x: Set instance_align on S390CPU TypeInfo target/riscv: Set instance_align on RISCVCPU TypeInfo target/ppc: Set instance_align on PowerPCCPU TypeInfo target/arm: Set instance_align on CPUARM TypeInfo qom: Allow objects to be allocated with increased alignment qom: Correct error values in two contracts qom: Clean up object_property_get_enum()'s error value qom: Correct object_class_dynamic_cast_assert() documentation sifive: Use DECLARE_*CHECKER* macros sifive: Move QOM typedefs and add missing includes sifive_u: Rename memmap enum constants sifive_e: Rename memmap enum constants
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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8063396b |
| 16-Sep-2020 |
Eduardo Habkost <ehabkost@redhat.com> |
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible.
$ ./scripts/codeconverter/converter.py -i \ --patte
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible.
$ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]')
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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#
f4ef8c9c |
| 11-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
QOM boilerplate cleanup
Documentation build fix: * memory: Remove kernel-doc comment marker (Eduardo Habk
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging
QOM boilerplate cleanup
Documentation build fix: * memory: Remove kernel-doc comment marker (Eduardo Habkost)
QOM cleanups: * Rename QOM macros for consistency between TYPE_* and type checking constants (Eduardo Habkost)
QOM new macros: * OBJECT_DECLARE_* and OBJECT_DEFINE_* macros (Daniel P. Berrangé) * DECLARE_*_CHECKER macros (Eduardo Habkost)
Automated QOM boilerplate changes: * Automated changes to use DECLARE_*_CHECKER (Eduardo Habkost * Automated changes to use OBJECT_DECLARE* (Eduardo Habkost)
# gpg: Signature made Thu 10 Sep 2020 19:17:49 BST # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6
* remotes/ehabkost/tags/machine-next-pull-request: (33 commits) virtio-vga: Use typedef name for instance_size vhost-user-vga: Use typedef name for instance_size xilinx_axienet: Use typedef name for instance_size lpc_ich9: Use typedef name for instance_size omap_intc: Use typedef name for instance_size xilinx_axidma: Use typedef name for instance_size tusb6010: Rename TUSB to TUSB6010 pc87312: Rename TYPE_PC87312_SUPERIO to TYPE_PC87312 vfio: Rename PCI_VFIO to VFIO_PCI usb: Rename USB_SERIAL_DEV to USB_SERIAL sabre: Rename SABRE_DEVICE to SABRE rs6000_mc: Rename RS6000MC_DEVICE to RS6000MC filter-rewriter: Rename FILTER_COLO_REWRITER to FILTER_REWRITER esp: Rename ESP_STATE to ESP ahci: Rename ICH_AHCI to ICH9_AHCI vmgenid: Rename VMGENID_DEVICE to TYPE_VMGENID vfio: Rename VFIO_AP_DEVICE_TYPE to TYPE_VFIO_AP_DEVICE dev-smartcard-reader: Rename CCID_DEV_NAME to TYPE_USB_CCID_DEV ap-device: Rename AP_DEVICE_TYPE to TYPE_AP_DEVICE gpex: Fix type checking function name ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
8110fa1d |
| 31-Aug-2020 |
Eduardo Habkost <ehabkost@redhat.com> |
Use DECLARE_*CHECKER* macros
Generated using:
$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]')
Reviewed-by: Daniel P. Berrangé <berrange@redha
Use DECLARE_*CHECKER* macros
Generated using:
$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]')
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-13-ehabkost@redhat.com> Message-Id: <20200831210740.126168-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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db1015e9 |
| 03-Sep-2020 |
Eduardo Habkost <ehabkost@redhat.com> |
Move QOM typedefs and add missing includes
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TY
Move QOM typedefs and add missing includes
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE.
Patch generated using:
$ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')
which will split "typdef struct { ... } TypedefName" declarations.
Followed by:
$ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]')
which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-10-ehabkost@redhat.com> Message-Id: <20200831210740.126168-11-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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f2a1cf91 |
| 10-Jul-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2020-07-07-v2' into staging
Error reporting patches patches for 2020-07-07
# gpg: Signature made Fri 10 Jul 2020 14:24:42 BST # gpg:
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2020-07-07-v2' into staging
Error reporting patches patches for 2020-07-07
# gpg: Signature made Fri 10 Jul 2020 14:24:42 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* remotes/armbru/tags/pull-error-2020-07-07-v2: (53 commits) xen: Use ERRP_GUARD() nbd: Use ERRP_GUARD() virtio-9p: Use ERRP_GUARD() fw_cfg: Use ERRP_GUARD() pflash: Use ERRP_GUARD() sd: Use ERRP_GUARD() scripts: Coccinelle script to use ERRP_GUARD() error: New macro ERRP_GUARD() hmp: Ignore Error objects where the return value suffices qdev: Ignore Error objects where the return value suffices qemu-img: Ignore Error objects where the return value suffices error: Avoid error_propagate() after migrate_add_blocker() qapi: Purge error_propagate() from QAPI core qapi: Smooth visitor error checking in generated code qapi: Smooth another visitor error checking pattern block/parallels: Simplify parallels_open() after previous commit error: Reduce unnecessary error propagation error: Eliminate error_propagate() manually error: Eliminate error_propagate() with Coccinelle, part 2 error: Eliminate error_propagate() with Coccinelle, part 1 ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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5325cc34 |
| 07-Jul-2020 |
Markus Armbruster <armbru@redhat.com> |
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in an unusual order:
void object_property_set_FOO(Object *obj, FOO_TY
qom: Put name parameter before value / visitor parameter
The object_property_set_FOO() setters take property name and value in an unusual order:
void object_property_set_FOO(Object *obj, FOO_TYPE value, const char *name, Error **errp)
Having to pass value before name feels grating. Swap them.
Same for object_property_set(), object_property_get(), and object_property_parse().
Convert callers with this Coccinelle script:
@@ identifier fun = { object_property_get, object_property_parse, object_property_set_str, object_property_set_link, object_property_set_bool, object_property_set_int, object_property_set_uint, object_property_set, object_property_set_qobject }; expression obj, v, name, errp; @@ - fun(obj, v, name, errp) + fun(obj, name, v, errp)
Chokes on hw/arm/musicpal.c's lcd_refresh() with the unhelpful error message "no position information". Convert that one manually.
Fails to convert hw/arm/armsse.c, because Coccinelle gets confused by ARMSSE being used both as typedef and function-like macro there. Convert manually.
Fails to convert hw/rx/rx-gdbsim.c, because Coccinelle gets confused by RXCPU being used both as typedef and function-like macro there. Convert manually. The other files using RXCPU that way don't need conversion.
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20200707160613.848843-27-armbru@redhat.com> [Straightforwad conflict with commit 2336172d9b "audio: set default value for pcspk.iobase property" resolved]
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#
6675a653 |
| 16-Jun-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/armbru/tags/pull-qom-2020-06-15' into staging
QOM patches for 2020-06-15
# gpg: Signature made Mon 15 Jun 2020 21:07:19 BST # gpg: using RSA key
Merge remote-tracking branch 'remotes/armbru/tags/pull-qom-2020-06-15' into staging
QOM patches for 2020-06-15
# gpg: Signature made Mon 15 Jun 2020 21:07:19 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* remotes/armbru/tags/pull-qom-2020-06-15: (84 commits) MAINTAINERS: Make section QOM cover hw/core/*bus.c as well qdev: qdev_init_nofail() is now unused, drop qdev: Convert bus-less devices to qdev_realize() with Coccinelle qdev: Use qdev_realize() in qdev_device_add() qdev: Make qdev_realize() support bus-less devices s390x/event-facility: Simplify creation of SCLP event devices microbit: Eliminate two local variables in microbit_init() sysbus: sysbus_init_child_obj() is now unused, drop sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 4 sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 3 sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2 sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1 qdev: Drop qdev_realize() support for null bus sysbus: Convert to sysbus_realize() etc. with Coccinelle sysbus: New sysbus_realize(), sysbus_realize_and_unref() sysbus: Tidy up sysbus_init_child_obj()'s @childsize arg, part 2 hw/arm/armsse: Pass correct child size to sysbus_init_child_obj() sysbus: Tidy up sysbus_init_child_obj()'s @childsize arg, part 1 microbit: Tidy up sysbus_init_child_obj() @child argument sysbus: Drop useless OBJECT() in sysbus_init_child_obj() calls ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
e9a82986 |
| 10-Jun-2020 |
Markus Armbruster <armbru@redhat.com> |
microbit: Eliminate two local variables in microbit_init()
Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Paolo Bonzini <p
microbit: Eliminate two local variables in microbit_init()
Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-53-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
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#
5a147c8c |
| 10-Jun-2020 |
Markus Armbruster <armbru@redhat.com> |
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 3
These are init/realize pairs produced by the previous commit's Coccinelle script where the argument test doesn't quite match. They
sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 3
These are init/realize pairs produced by the previous commit's Coccinelle script where the argument test doesn't quite match. They need even more careful review.
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-50-armbru@redhat.com>
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#
b0d09949 |
| 10-Jun-2020 |
Markus Armbruster <armbru@redhat.com> |
microbit: Tidy up sysbus_init_child_obj() @child argument
The callers of sysbus_init_child_obj() commonly pass either &child, sizeof(child), or pchild, sizeof(*pchild). Tidy up two that don't, most
microbit: Tidy up sysbus_init_child_obj() @child argument
The callers of sysbus_init_child_obj() commonly pass either &child, sizeof(child), or pchild, sizeof(*pchild). Tidy up two that don't, mostly to keep future commits simpler.
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200610053247.1583243-41-armbru@redhat.com>
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Revision tags: v5.0.0, v4.2.0 |
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#
95a9457f |
| 16-Aug-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/armbru/tags/pull-include-2019-08-13-v2' into staging
Header cleanup patches for 2019-08-13
# gpg: Signature made Fri 16 Aug 2019 12:39:12 BST # gpg:
Merge remote-tracking branch 'remotes/armbru/tags/pull-include-2019-08-13-v2' into staging
Header cleanup patches for 2019-08-13
# gpg: Signature made Fri 16 Aug 2019 12:39:12 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* remotes/armbru/tags/pull-include-2019-08-13-v2: (29 commits) sysemu: Split sysemu/runstate.h off sysemu/sysemu.h sysemu: Move the VMChangeStateEntry typedef to qemu/typedefs.h Include sysemu/sysemu.h a lot less Clean up inclusion of sysemu/sysemu.h numa: Move remaining NUMA declarations from sysemu.h to numa.h Include sysemu/hostmem.h less numa: Don't include hw/boards.h into sysemu/numa.h Include hw/boards.h a bit less Include hw/qdev-properties.h less Include qemu/main-loop.h less Include qemu/queue.h slightly less Include hw/hw.h exactly where needed Include qom/object.h slightly less Include exec/memory.h slightly less Include migration/vmstate.h less migration: Move the VMStateDescription typedef to typedefs.h Clean up inclusion of exec/cpu-common.h Include hw/irq.h a lot less typedefs: Separate incomplete types and function types ide: Include hw/ide/internal a bit less outside hw/ide/ ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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a27bd6c7 |
| 12-Aug-2019 |
Markus Armbruster <armbru@redhat.com> |
Include hw/qdev-properties.h less
In my "build everything" tree, changing hw/qdev-properties.h triggers a recompile of some 2700 out of 6600 objects (not counting tests and objects that don't depend
Include hw/qdev-properties.h less
In my "build everything" tree, changing hw/qdev-properties.h triggers a recompile of some 2700 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h).
Many places including hw/qdev-properties.h (directly or via hw/qdev.h) actually need only hw/qdev-core.h. Include hw/qdev-core.h there instead.
hw/qdev.h is actually pointless: all it does is include hw/qdev-core.h and hw/qdev-properties.h, which in turn includes hw/qdev-core.h. Replace the remaining uses of hw/qdev.h by hw/qdev-properties.h.
While there, delete a few superfluous inclusions of hw/qdev-core.h.
Touching hw/qdev-properties.h now recompiles some 1200 objects.
Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Daniel P. Berrangé" <berrange@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20190812052359.30071-22-armbru@redhat.com>
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ceac83e9 |
| 24-May-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190523' into staging
target-arm queue: * exynos4210: QOM'ify the Exynos4210 SoC * exynos4210: Add DMA support for the Exynos42
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190523' into staging
target-arm queue: * exynos4210: QOM'ify the Exynos4210 SoC * exynos4210: Add DMA support for the Exynos4210 * arm_gicv3: Fix writes to ICC_CTLR_EL3 * arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1} * target/arm: Fix vector operation segfault * target/arm: Minor improvements to BFXIL, EXTR
# gpg: Signature made Thu 23 May 2019 15:22:55 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190523: hw/arm/exynos4210: QOM'ify the Exynos4210 SoC hw/arm/exynos4210: Add DMA support for the Exynos4210 hw/arm/exynos4: Use the IEC binary prefix definitions hw/arm/exynos4: Remove unuseful debug code hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3 hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1} arm: Rename hw/arm/arm.h to hw/arm/boot.h arm: Remove unnecessary includes of hw/arm/arm.h arm: Move system_clock_scale to armv7m_systick.h target/arm: Fix vector operation segfault target/arm: Simplify BFXIL expansion target/arm: Use extract2 for EXTR
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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12ec8bd5 |
| 23-May-2019 |
Peter Maydell <peter.maydell@linaro.org> |
arm: Rename hw/arm/arm.h to hw/arm/boot.h
The header file hw/arm/arm.h now includes only declarations relating to hw/arm/boot.c functionality. Rename it accordingly, and adjust its header comment.
arm: Rename hw/arm/arm.h to hw/arm/boot.h
The header file hw/arm/arm.h now includes only declarations relating to hw/arm/boot.c functionality. Rename it accordingly, and adjust its header comment.
The bulk of this commit was created via perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
In a few cases we can just delete the #include: hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and include/hw/arm/bcm2836.h did not require it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
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Revision tags: v4.0.0, v4.0.0-rc1, v4.0.0-rc0 |
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b4fbe1f6 |
| 29-Jan-2019 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190129' into staging
target-arm queue: * Fix validation of 32-bit address spaces for aa32 (fixes an assert introduced in ba97be
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190129' into staging
target-arm queue: * Fix validation of 32-bit address spaces for aa32 (fixes an assert introduced in ba97be9f4a4) * v8m: Ensure IDAU is respected if SAU is disabled * gdbstub: fix gdb_get_cpu(s, pid, tid) when pid and/or tid are 0 * exec.c: Use correct attrs in cpu_memory_rw_debug() * accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write * target/arm: Don't clear supported PMU events when initializing PMCEID1 * memory: add memory_region_flush_rom_device() * microbit: Add stub NRF51 TWI magnetometer/accelerometer detection * tests/microbit-test: extend testing of microbit devices * checkpatch: Don't emit spurious warnings about block comments * aspeed/smc: misc bug fixes * xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs * xlnx-zynqmp: Realize cluster after putting RPUs in it * accel/tcg: Add cluster number to TCG TB hash so differently configured CPUs don't pick up cached TBs for the wrong kind of CPU
# gpg: Signature made Tue 29 Jan 2019 11:59:10 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20190129: (23 commits) gdbstub: Simplify gdb_get_cpu_pid() to use cpu->cluster_index accel/tcg: Add cluster number to TCG TB hash qom/cpu: Add cluster_index to CPUState hw/arm/xlnx-zynqmp: Realize cluster after putting RPUs in it aspeed/smc: snoop SPI transfers to fake dummy cycles aspeed/smc: Add dummy data register aspeed/smc: define registers for all possible CS aspeed/smc: fix default read value xlnx-zynqmp: Don't create rpu-cluster if there are no RPUs checkpatch: Don't emit spurious warnings about block comments tests/microbit-test: Check nRF51 UART functionality tests/microbit-test: Make test independent of global_qtest tests/libqtest: Introduce qtest_init_with_serial() memory: add memory_region_flush_rom_device() target/arm: Don't clear supported PMU events when initializing PMCEID1 MAINTAINERS: update microbit ARM board files accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write exec.c: Use correct attrs in cpu_memory_rw_debug() tests/microbit-test: add TWI stub device test arm: Stub out NRF51 TWI magnetometer/accelerometer detection ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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9d68bf56 |
| 29-Jan-2019 |
Steffen Görtz <contrib@steffen-goertz.de> |
arm: Stub out NRF51 TWI magnetometer/accelerometer detection
Recent microbit firmwares panic if the TWI magnetometer/accelerometer devices are not detected during startup. We don't implement TWI (I
arm: Stub out NRF51 TWI magnetometer/accelerometer detection
Recent microbit firmwares panic if the TWI magnetometer/accelerometer devices are not detected during startup. We don't implement TWI (I2C) so let's stub out these devices just to let the firmware boot.
Signed-off by: Steffen Görtz <contrib@steffen-goertz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190110094020.18354-2-stefanha@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed comment style] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v3.1.0, v3.1.0-rc5, v3.1.0-rc4, v3.1.0-rc3, v3.1.0-rc2, v3.1.0-rc1, v3.1.0-rc0 |
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7d56239f |
| 02-Nov-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181102' into staging
target-arm queue: * microbit: Add the UART to our nRF51 SoC model * Add a virtual Xilinx Versal board "xl
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181102' into staging
target-arm queue: * microbit: Add the UART to our nRF51 SoC model * Add a virtual Xilinx Versal board "xlnx-versal-virt" * hw/arm/virt: Set VIRT_COMPAT_3_0 compat * MAINTAINERS: Remove bouncing email in ARM ACPI * strongarm: mask off high[31:28] bits from dir and state registers * target/arm: Conditionalize some asserts on aarch32 support * hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro
# gpg: Signature made Fri 02 Nov 2018 17:14:43 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20181102: hw/arm: versal: Add a virtual Xilinx Versal board hw/arm: versal: Add a model of Xilinx Versal SoC target/arm: Conditionalize some asserts on aarch32 support hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro strongarm: mask off high[31:28] bits from dir and state registers MAINTAINERS: Remove bouncing email in ARM ACPI tests/boot-serial-test: Add microbit board testcase hw/arm/nrf51_soc: Connect UART to nRF51 SoC hw/char: Implement nRF51 SoC UART hw/arm/virt: Set VIRT_COMPAT_3_0 compat
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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b0014913 |
| 30-Oct-2018 |
Julia Suvorova <jusual@mail.ru> |
hw/arm/nrf51_soc: Connect UART to nRF51 SoC
Wire up nRF51 UART in the corresponding SoC.
Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-b
hw/arm/nrf51_soc: Connect UART to nRF51 SoC
Wire up nRF51 UART in the corresponding SoC.
Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: libfdt-20181002 |
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71fbecea |
| 25-Sep-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180925-1' into staging
target-arm queue: * target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs * hw/arm/exynos4210: fix Ex
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180925-1' into staging
target-arm queue: * target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs * hw/arm/exynos4210: fix Exynos4210 UART support * hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes * arm: Add BBC micro:bit machine * aspeed/i2c: Fix interrupt handling bugs * hw/arm/smmu-common: Fix the name of the iommu memory regions * hw/arm/smmuv3: fix eventq recording and IRQ triggerring * hw/intc/arm_gic: Document QEMU interface * hw/intc/arm_gic: Drop GIC_BASE_IRQ macro * hw/net/pcnet-pci: Convert away from old_mmio accessors * hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements * aspeed/timer: fix compile breakage with clang 3.4.2 * hw/arm/aspeed: change the FMC flash model of the AST2500 evb * hw/arm/aspeed: Minor code cleanups * target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode
# gpg: Signature made Tue 25 Sep 2018 15:23:11 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180925-1: (21 commits) target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode aspeed/smc: fix some alignment issues hw/arm/aspeed: Add an Aspeed machine class hw/arm/aspeed: change the FMC flash model of the AST2500 evb aspeed/timer: fix compile breakage with clang 3.4.2 hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write hw/net/pcnet-pci: Convert away from old_mmio accessors hw/intc/arm_gic: Drop GIC_BASE_IRQ macro hw/intc/arm_gic: Document QEMU interface hw/arm/smmuv3: fix eventq recording and IRQ triggerring hw/arm/smmu-common: Fix the name of the iommu memory regions aspeed/i2c: Fix receive done interrupt handling aspeed/i2c: Handle receive command in separate function aspeed/i2c: interrupts should be cleared by software only arm: Add BBC micro:bit machine arm: Add Nordic Semiconductor nRF51 SoC MAINTAINERS: Add NRF51 entry hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes hw/arm/exynos4210: fix Exynos4210 UART support ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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b148ed46 |
| 25-Sep-2018 |
Joel Stanley <joel@jms.id.au> |
arm: Add BBC micro:bit machine
This adds the base for a machine model of the BBC micro:bit:
https://en.wikipedia.org/wiki/Micro_Bit
This is a system with a nRF51 SoC containing the main processo
arm: Add BBC micro:bit machine
This adds the base for a machine model of the BBC micro:bit:
https://en.wikipedia.org/wiki/Micro_Bit
This is a system with a nRF51 SoC containing the main processor, with various peripherals on board.
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20180831220920.27113-4-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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