hw/arm/boot: always clear r0 when booting kernels

The 32-bit ARM Linux kernel booting ABI requires that r0 is 0
when calling the kernel image. A bug in commit 10b8ec73e610e01
meant that for boards w

hw/arm/boot: always clear r0 when booting kernels

The 32-bit ARM Linux kernel booting ABI requires that r0 is 0
when calling the kernel image. A bug in commit 10b8ec73e610e01
meant that for boards which use the write_board_setup hook (which
means "highbank", "midway", "raspi2" and "xilinx-zynq-a9") we
were incorrectly skipping the "clear r0" instruction in the
mini-bootloader. Use the right offset in the "add lr, pc, #n"
instruction so that we return from the board-setup code to the
correct place.

Signed-off-by: Sylvain Garrigues <sylvain@sylvaingarrigues.com>
[PMM: Expanded commit message]
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

* Log filtering from Alex and Peter
* Chardev fix from Marc-André
* config.status tweak from David
* Header file tweaks

Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

* Log filtering from Alex and Peter
* Chardev fix from Marc-André
* config.status tweak from David
* Header file tweaks from Markus, myself and Veronia (Outreachy candidate)
* get_ticks_per_sec() removal from Rutuja (Outreachy candidate)
* Coverity fix from myself
* PKE implementation from myself, based on rth's XSAVE support

# gpg: Signature made Thu 24 Mar 2016 20:15:11 GMT using RSA key ID 78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>"

* remotes/bonzini/tags/for-upstream: (28 commits)
target-i386: implement PKE for TCG
config.status: Pass extra parameters
char: translate from QIOChannel error to errno
exec: fix error handling in file_ram_alloc
cputlb: modernise the debug support
qemu-log: support simple pid substitution for logs
target-arm: dfilter support for in_asm
qemu-log: dfilter-ise exec, out_asm, op and opt_op
qemu-log: new option -dfilter to limit output
qemu-log: Improve the "exec" TB execution logging
qemu-log: Avoid function call for disabled qemu_log_mask logging
qemu-log: correct help text for -d cpu
tcg: pass down TranslationBlock to tcg_code_gen
util: move declarations out of qemu-common.h
Replaced get_tick_per_sec() by NANOSECONDS_PER_SECOND
hw: explicitly include qemu-common.h and cpu.h
include/crypto: Include qapi-types.h or qemu/bswap.h instead of qemu-common.h
isa: Move DMA_transfer_handler from qemu-common.h to hw/isa/isa.h
Move ParallelIOArg from qemu-common.h to sysemu/char.h
Move QEMU_ALIGN_*() from qemu-common.h to qemu/osdep.h
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Conflicts:
scripts/clean-includes

show more ...

include/qemu/osdep.h: Don't include qapi/error.h

Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its fi

include/qemu/osdep.h: Don't include qapi/error.h

Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.

Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.

Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.

This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160304' into staging

target-arm queue:
* Correct handling of writes to CPSR from gdbstub in user mode
* virt: lift maximum RAM

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160304' into staging

target-arm queue:
* Correct handling of writes to CPSR from gdbstub in user mode
* virt: lift maximum RAM limit to 255GB
* sdhci: implement reset
* virt: if booting in Secure mode, provide secure-only RAM, make first
flash device secure-only, and assume the EL3 boot rom will handle PSCI
* bcm2835: use explicit endianness accessors rather than ldl/stl_phys
* support big-endian in system mode for ARM
* implement SETEND instruction
* arm_gic: implement the GICv2 GICC_DIR register
* fix SRS bug: only trap from S-EL1 to EL3 if specified mode is Mon

# gpg: Signature made Fri 04 Mar 2016 11:38:53 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20160304: (30 commits)
target-arm: Only trap SRS from S-EL1 if specified mode is MON
hw/intc/arm_gic.c: Implement GICv2 GICC_DIR
arm: boot: Support big-endian elfs
loader: Add data swap option to load-elf
loader: load_elf(): Add doc comment
loader: add API to load elf header
target-arm: implement BE32 mode in system emulation
target-arm: implement setend
target-arm: introduce tbflag for endianness
target-arm: a64: Add endianness support
target-arm: introduce disas flag for endianness
target-arm: pass DisasContext to gen_aa32_ld*/st*
target-arm: implement SCTLR.EE
linux-user: arm: handle CPSR.E correctly in strex emulation
linux-user: arm: set CPSR.E/SCTLR.E0E correctly for BE mode
arm: cpu: handle BE32 user-mode as BE
target-arm: cpu: Move cpu_is_big_endian to header
target-arm: implement SCTLR.B, drop bswap_code
linux-user: arm: pass env to get_user_code_*
linux-user: arm: fix coding style for some linux-user signal functions
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

arm: boot: Support big-endian elfs

Support ARM big-endian ELF files in system-mode emulation. When loading
an elf, determine the endianness mode expected by the elf, and set the
relevant CPU state a

arm: boot: Support big-endian elfs

Support ARM big-endian ELF files in system-mode emulation. When loading
an elf, determine the endianness mode expected by the elf, and set the
relevant CPU state accordingly.

With this, big-endian modes are now fully supported via system-mode LE,
so there is no need to restrict the elf loading to the TARGET
endianness so the ifdeffery on TARGET_WORDS_BIGENDIAN goes away.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: fix typo in comments]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

loader: Add data swap option to load-elf

Some CPUs are of an opposite data-endianness to other components in the
system. Sometimes elfs have the data sections layed out with this CPU
data-endianness

loader: Add data swap option to load-elf

Some CPUs are of an opposite data-endianness to other components in the
system. Sometimes elfs have the data sections layed out with this CPU
data-endianness accounting for when loaded via the CPU, so byte swaps
(relative to other system components) will occur.

The leading example, is ARM's BE32 mode, which is is basically LE with
address manipulation on half-word and byte accesses to access the
hw/byte reversed address. This means that word data is invariant
across LE and BE32. This also means that instructions are still LE.
The expectation is that the elf will be loaded via the CPU in this
endianness scheme, which means the data in the elf is reversed at
compile time.

As QEMU loads via the system memory directly, rather than the CPU, we
need a mechanism to reverse elf data endianness to implement this
possibility.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20160219.1' into staging

VFIO updates 2016-02-19

- AER pre-enable and misc fixes (Cao jin and Chen Fan)
- PCI_CAP_LIST_NEXT & PCI_M

Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20160219.1' into staging

VFIO updates 2016-02-19

- AER pre-enable and misc fixes (Cao jin and Chen Fan)
- PCI_CAP_LIST_NEXT & PCI_MSIX_FLAGS cleanup (Wei Yang)
- AMD XGBE KVM platform passthrough (Eric Auger)

# gpg: Signature made Fri 19 Feb 2016 17:28:36 GMT using RSA key ID 3BB08B22
# gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>"
# gpg: aka "Alex Williamson <alex@shazbot.org>"
# gpg: aka "Alex Williamson <alwillia@redhat.com>"
# gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>"

* remotes/awilliam/tags/vfio-update-20160219.1:
vfio/pci: use PCI_MSIX_FLAGS on retrieving the MSIX entries
hw/arm/sysbus-fdt: remove qemu_fdt_setprop returned value check
hw/arm/sysbus-fdt: enable amd-xgbe dynamic instantiation
hw/arm/sysbus-fdt: helpers for clock node generation
device_tree: qemu_fdt_getprop_cell converted to use the error API
device_tree: qemu_fdt_getprop converted to use the error API
device_tree: introduce qemu_fdt_node_path
device_tree: introduce load_device_tree_from_sysfs
hw/vfio/platform: amd-xgbe device
vfio/pci: replace 1 with PCI_CAP_LIST_NEXT to make code self-explain
pcie_aer: expose pcie_aer_msg() interface
aer: impove pcie_aer_init to support vfio device
vfio: make the 4 bytes aligned for capability size
pcie: modify the capability size assert

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

device_tree: qemu_fdt_getprop_cell converted to use the error API

This patch aligns the prototype with qemu_fdt_getprop. The caller
can choose whether the function self-asserts on error (passing
&er

device_tree: qemu_fdt_getprop_cell converted to use the error API

This patch aligns the prototype with qemu_fdt_getprop. The caller
can choose whether the function self-asserts on error (passing
&error_fatal as Error ** argument, corresponding to the legacy behavior),
or behaves differently such as simply output a message.

In this later case the caller can use the new lenp parameter to interpret
the error if any.

Signed-off-by: Eric Auger <eric.auger@linaro.org>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>

show more ...

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160203' into staging

target-arm queue:
* virt-acpi-build: add always-on property for timer
* various fixes for EL2 and EL3 beh

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160203' into staging

target-arm queue:
* virt-acpi-build: add always-on property for timer
* various fixes for EL2 and EL3 behaviour
* arm: virt-acpi: each MADT.GICC entry as enabled unconditionally
* target-arm: Don't report presence of EL2 if it doesn't exist
* raspi: add raspberry pi 2 machine

# gpg: Signature made Wed 03 Feb 2016 18:58:02 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20160203:
raspi: add raspberry pi 2 machine
arm/boot: move highbank secure board setup code to common routine
bcm2836: add bcm2836 SoC device
bcm2836_control: add bcm2836 ARM control logic
bcm2835_peripherals: add rollup device for bcm2835 peripherals
bcm2835_ic: add bcm2835 interrupt controller
bcm2835_property: add bcm2835 property channel
bcm2835_mbox: add BCM2835 mailboxes
target-arm: Don't report presence of EL2 if it doesn't exist
libvixl: Avoid std::abs() of 64-bit type
arm: virt-acpi: each MADT.GICC entry as enabled unconditionally
target-arm: Implement the S2 MMU inputsize > pamax check
target-arm: Rename check_s2_startlevel to check_s2_mmu_setup
target-arm: Apply S2 MMU startlevel table size check to AArch64
hw/arm: Setup EL1 and EL2 in AArch64 mode for 64bit Linux boots
target-arm: Make various system registers visible to EL3
virt-acpi-build: add always-on property for timer

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

arm/boot: move highbank secure board setup code to common routine

The new version is slightly different, to support Rasbperry Pi (in
particular, Pi1's arm11 core which doesn't support v7 instruction

arm/boot: move highbank secure board setup code to common routine

The new version is slightly different, to support Rasbperry Pi (in
particular, Pi1's arm11 core which doesn't support v7 instructions
such as MOVW).

Tested-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/arm: Setup EL1 and EL2 in AArch64 mode for 64bit Linux boots

When booting Linux on AArch64 enabled cores, setup EL1 and
EL2 to use AArch64.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilin

hw/arm: Setup EL1 and EL2 in AArch64 mode for 64bit Linux boots

When booting Linux on AArch64 enabled cores, setup EL1 and
EL2 to use AArch64.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/arm: Clean up includes

Clean up includes so that osdep.h is included first and headers
which it implies are not included manually.

This commit was created with scripts/clean-includes.

Signed-of

hw/arm: Clean up includes

Clean up includes so that osdep.h is included first and headers
which it implies are not included manually.

This commit was created with scripts/clean-includes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1449505425-32022-4-git-send-email-peter.maydell@linaro.org

show more ...

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151110' into staging

target-arm queue:
* fix bugs in gdb singlestep handling and breakpoints
* minor code cleanup in arm_gic

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151110' into staging

target-arm queue:
* fix bugs in gdb singlestep handling and breakpoints
* minor code cleanup in arm_gic
* clean up error messages in hw/arm/virt
* fix highbank kernel booting by adding a board-setup blob

# gpg: Signature made Tue 10 Nov 2015 13:43:52 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20151110:
target-arm: Clean up DISAS_UPDATE usage in AArch32 translation code
hw/arm/virt: error_report cleanups
arm: highbank: Implement PSCI and dummy monitor
arm: highbank: Defeature CPU override
arm: boot: Add secure_board_setup flag
hw/intc/arm_gic: Remove the definition of NUM_CPU
target-arm: Fix gdb singlestep handling in arm_debug_excp_handler()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

arm: boot: Add secure_board_setup flag

Add a flag that when set, will cause the primary CPU to start in secure
mode, even if the overall boot is non-secure. This is useful for when
there is a board-

arm: boot: Add secure_board_setup flag

Add a flag that when set, will cause the primary CPU to start in secure
mode, even if the overall boot is non-secure. This is useful for when
there is a board-setup blob that needs to run from secure mode, but
device and secondary CPU init should still be done as-normal for a non-
secure boot.

Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: d1170774d5446d715fced7739edfc61a5be931f9.1447007690.git.crosthwaite.peter@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151103' into staging

target-arm queue:
* code cleanup to use symbolic constants for register bank numbers
* fix direct booting

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20151103' into staging

target-arm queue:
* code cleanup to use symbolic constants for register bank numbers
* fix direct booting of modern Linux kernels on xilinx_zynq by setting
SCLR values to what the kernel expects firmware to have done
* implement SYSRESETREQ for ARMv7M CPU (stellaris boards)
* update MAINTAINERS to mention new qemu-arm mailing list
* clean up display of PSTATE in AArch64 debug logs
* report Secure/Nonsecure status in CPU debug logs
* fix a missing _CCA attribute in ACPI tables
* add support for GICv3 to ACPI tables

# gpg: Signature made Tue 03 Nov 2015 13:58:46 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20151103:
ARM: ACPI: Fix MPIDR value in ACPI table
hw/arm/virt-acpi-build: Add GICC ACPI subtable for GICv3
hw/arm/virt-acpi-build: _CCA attribute is compulsory
target-arm: Report S/NS status in the CPU debug logs
target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32
MAINTAINERS: Add new qemu-arm mailing list to ARM related entries
arm: stellaris: exit on external reset request
armv7-m: Implement SYSRESETREQ
armv7-m: Return DeviceState* from armv7m_init()
arm: xilinx_zynq: Add linux pre-boot
arm: boot: Add board specific setup code API
arm: boot: Adjust indentation of FIXUP comments
target-arm: Add and use symbolic names for register banks

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

arm: boot: Add board specific setup code API

Add an API for boards to inject their own preboot software (or
firmware) sequence.

The software then returns to the bootloader via the link register. Th

arm: boot: Add board specific setup code API

Add an API for boards to inject their own preboot software (or
firmware) sequence.

The software then returns to the bootloader via the link register. This
allows boards to do their own little bits of firmware setup without
needed to replace the bootloader completely (which is the requirement
for existing firmware support).

The blob is loaded by a callback if and only if doing a linux boot
(similar to the existing write_secondary support).

Rewrite the comment for the primary boot blob.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: 070295644c6ac84696d743913296e8cfefb48c15.1446182614.git.crosthwaite.peter@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

arm: boot: Adjust indentation of FIXUP comments

These comments start immediately after the current longest name in the
list. Tab them out to the next tab stop to give a little breathing room
and pre

arm: boot: Adjust indentation of FIXUP comments

These comments start immediately after the current longest name in the
list. Tab them out to the next tab stop to give a little breathing room
and prepare for FIXUP_BOARD_SETUP which will require more indent.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
Message-id: b9b9bb8f1c307c1ef8a3f26ff1f34fabb34b332e.1446182614.git.crosthwaite.peter@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150908' into staging

target-arm queue:
* Implement priority handling properly via GICC_APR
* Enable TZ extensions on the GIC i

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150908' into staging

target-arm queue:
* Implement priority handling properly via GICC_APR
* Enable TZ extensions on the GIC if we're using them
* Minor preparatory patches for EL3 support
* cadence_gem: Correct Marvell PHY SPCFC reset value
* Support AHCI in ZynqMP

# gpg: Signature made Tue 08 Sep 2015 17:48:33 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20150908:
xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP
xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort
ahci.c: Don't assume AHCIState's parent is AHCIPCIState
ahci: Separate the AHCI state structure into the header
cadence_gem: Correct Marvell PHY SPCFC reset value
target-arm: Add AArch64 access to PAR_EL1
target-arm: Correct opc1 for AT_S12Exx
target-arm: Log the target EL when taking exceptions
target-arm: Fix default_exception_el() function for the case when EL3 is not supported
hw/arm/virt: Enable TZ extensions on the GIC if we are using them
hw/arm/virt: Default to not providing TrustZone support
hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs
hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot
hw/arm: new interface for devices which need to behave differently for kernel boot
qom: Add recursive version of object_child_for_each
hw/intc/arm_gic: Actually set the active bits for active interrupts
hw/intc/arm_gic: Drop running_irq and last_active arrays
hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registers
hw/intc/arm_gic: Running priority is group priority, not full priority
armv7m_nvic: Implement ICSR without using internal GIC state

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/arm: new interface for devices which need to behave differently for kernel boot

For ARM we have a little minimalist bootloader in hw/arm/boot.c which
takes the place of firmware if we're directly

hw/arm: new interface for devices which need to behave differently for kernel boot

For ARM we have a little minimalist bootloader in hw/arm/boot.c which
takes the place of firmware if we're directly booting a Linux kernel.
Unfortunately a few devices need special case handling in this situation
to do the initialization which on real hardware would be done by
firmware. (In particular if we're booting a kernel in NonSecure state
then we need to make a TZ-aware GIC put all its interrupts into Group 1,
or the guest will be unable to use them.)

Create a new QOM interface which can be implemented by devices which
need to do something different from their default reset behaviour.
The callback will be called after machine initialization and before
first reset.

Suggested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1441383782-24378-3-git-send-email-peter.maydell@linaro.org

show more ...

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150715' into staging

target arm queue:
* handle broken AArch64 kernels which assume DTB won't cross a 2MB boundary
* correct b

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150715' into staging

target arm queue:
* handle broken AArch64 kernels which assume DTB won't cross a 2MB boundary
* correct broken SCTLR_EL3 reset value

# gpg: Signature made Wed Jul 15 17:24:24 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20150715:
hw/arm/boot: Increase fdt alignment
target-arm: Fix broken SCTLR_EL3 reset

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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hw/arm/boot: Increase fdt alignment

The Linux kernel on aarch64 creates a page table entry at early bootup
that spans the 2MB range on memory spanning the fdt start address:

[ ALIGN_DOWN(fdt, 2MB

hw/arm/boot: Increase fdt alignment

The Linux kernel on aarch64 creates a page table entry at early bootup
that spans the 2MB range on memory spanning the fdt start address:

[ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ]

This means that when our current 4k alignment happens to fall at the end
of the aligned region, Linux tries to access memory that is not mapped.

The easy fix is to instead increase the alignment to 2MB, making Linux's
logic always succeed.

We leave the existing 4k alignment for 32bit kernels to not cause any
regressions due to space constraints.

Reported-by: Andreas Schwab <schwab@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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Merge remote-tracking branch 'remotes/afaerber/tags/qom-cpu-for-peter' into staging

QOM CPUState and X86CPU

* Further QOM'ification of CPU initialization
* Propagation of CPUState arguments and eli

Merge remote-tracking branch 'remotes/afaerber/tags/qom-cpu-for-peter' into staging

QOM CPUState and X86CPU

* Further QOM'ification of CPU initialization
* Propagation of CPUState arguments and elimination of ENV_GET_CPU() usage
* cpu_set_pc() abstraction
* CPUClass::disas_set_info() hook

# gpg: Signature made Thu Jul 9 14:23:12 2015 BST using RSA key ID 3E7E013F
# gpg: Good signature from "Andreas Färber <afaerber@suse.de>"
# gpg: aka "Andreas Färber <afaerber@suse.com>"

* remotes/afaerber/tags/qom-cpu-for-peter: (22 commits)
disas: cris: QOMify target specific disas setup
disas: cris: Fix 0 buffer length case
disas: microblaze: QOMify target specific disas setup
disas: arm: QOMify target specific disas setup
disas: arm-a64: Make printfer and stream variable
disas: QOMify target specific setup
disas: Add print_insn to disassemble info
microblaze: boot: Use cpu_set_pc()
hw/arm/boot: Use cpu_set_pc()
gdbstub: Use cpu_set_pc() helper
cpu: Add wrapper for the set_pc() hook
cpu-exec: Purge all uses of ENV_GET_CPU()
cpu: Change cpu_exec_init() arg to cpu, not env
cpu: Change tcg_cpu_exec() arg to cpu, not env
gdbstub: Change gdbserver_fork() to accept cpu instead of env
translate-all: Change tb_flush() env argument to cpu
target-ppc: Move cpu_exec_init() call to realize function
cpu: Convert cpu_index into a bitmap
cpu: Add Error argument to cpu_exec_init()
cpu: Reorder cpu->as, cpu->thread_id, cpu->memory_dispatch init
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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hw/arm/boot: Use cpu_set_pc()

Use cpu_set_pc() across the board for setting program counters. This
removes instances of system level code having to reach into the CPU
env.

Reviewed-by: Peter Maydel

hw/arm/boot: Use cpu_set_pc()

Use cpu_set_pc() across the board for setting program counters. This
removes instances of system level code having to reach into the CPU
env.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
[AF: Avoid repeated casts with local variables]
Signed-off-by: Andreas Färber <afaerber@suse.de>

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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150615' into staging

target-arm queue:
* Handle "extended small page" descriptors correctly
* Use extended address bits from s

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150615' into staging

target-arm queue:
* Handle "extended small page" descriptors correctly
* Use extended address bits from supersection short descriptors
* Update interrupt status for all cores in gic_update
* Fix off-by-one in exynos4210_fimd bit-swap code
* Remove stray unused 'pending_exception' field
* Add Cortex-A53 KVM support
* Fix reset value of REVIDR
* Add AArch32 MIDR aliases for ARMv8 cores
* MAINTAINERS update for ARM ACPI code
* Trust the kernel's value of MPIDR if we're using KVM
* Various pxa2xx device updates to avoid old APIs
* Mark pxa2xx copro registers as ARM_CP_IO so -icount works
* Correctly UNDEF Thumb2 DSP insns on Cortex-M3
* Initial work towards implementing PMSAv7
* Fix a reset order bug introduced recently
* Correct "preferred return address" for cpreg access exceptions
* Add ACPI SPCR table for the virt board

# gpg: Signature made Mon Jun 15 18:19:34 2015 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20150615: (28 commits)
hw/arm/virt-acpi-build: Add SPCR table
ACPI: Add definitions for the SPCR table
target-arm: Correct "preferred return address" for cpreg access exceptions
hw/arm/boot: fix rom_reset notifier registration order
arm: helper: rename get_phys_addr_mpu
arm: Add has-mpu property
arm: Implement uniprocessor with MP config
arm: Refactor get_phys_addr FSR return mechanism
arm: helper: Factor out CP regs common to [pv]msa
arm: Don't add v7mp registers in MPU systems
arm: Do not define TLBTR in PMSA systems
target-arm: Add the THUMB_DSP feature
hw/sd/pxa2xx_mmci: Stop using old_mmio in MemoryRegionOps
hw/arm/pxa2xx: Convert pxa2xx-ssp to VMState
hw/arm/pxa2xx: Add reset method for pxa2xx_ssp
hw/arm/pxa2xx: Convert pxa2xx-fir to QOM and VMState
hw/arm/pxa2xx: Mark coprocessor registers as ARM_CP_IO
target-arm: Use the kernel's idea of MPIDR if we're using KVM
MAINTAINERS: Add myself as ARM ACPI Subsystem maintainer
target-arm: add AArch32 MIDR aliases in ARMv8
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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hw/arm/boot: fix rom_reset notifier registration order

commit ac9d32e39664e060cd1b538ff190980d57ad69e4 had the consequence to
register the do_cpu_reset after the rom_reset one. Hence they get
execut

hw/arm/boot: fix rom_reset notifier registration order

commit ac9d32e39664e060cd1b538ff190980d57ad69e4 had the consequence to
register the do_cpu_reset after the rom_reset one. Hence they get
executed in the wrong order. This commit restores the registration of
do_cpu_reset in arm_load_kernel.

Signed-off-by: Eric Auger <eric.auger@linaro.org>
Reported-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Tested-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1434111582-9325-1-git-send-email-eric.auger@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

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