History log of /openbmc/qemu/hw/arm/aspeed_ast27x0-ssp.c (Results 1 – 6 of 6)
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Revision tags: v10.0.2, v10.0.1, v10.0.0, v9.2.3
# e381338d 13-Mar-2025 Steven Lee <steven_lee@aspeedtech.com>

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC

The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:

- De

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC

The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:

- Defined IRQ maps for AST27x0 A1 SSP SoC
- Implemented initialization functions

The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt controller.

Difference from AST2700:

- AST2700
- Support GICINT128 to GICINT136 in INTC
- The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196

- AST2700-ssp
- Support SSPINT128 to SSPINT136 in INTC
- The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Ic5121dd78c5dacf1ec4b4e791cc7bf476a8b608f
Link: https://lore.kernel.org/qemu-devel/20250313054020.2583556-7-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

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# 35f94ee8 13-Mar-2025 Steven Lee <steven_lee@aspeedtech.com>

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC

AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:

- Introduce Aspeed2

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC

AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:

- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A0 SSP SoC
- Implement initialization and realization functions
- Add support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: If83e752873af393f3b71249176454399de0be40f
Link: https://lore.kernel.org/qemu-devel/20250313054020.2583556-6-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

show more ...


# 74432587 13-Mar-2025 Steven Lee <steven_lee@aspeedtech.com>

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC

The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:

- De

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC

The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:

- Defined IRQ maps for AST27x0 A1 SSP SoC
- Implemented initialization functions

The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt controller.

Difference from AST2700:

- AST2700
- Support GICINT128 to GICINT136 in INTC
- The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196

- AST2700-ssp
- Support SSPINT128 to SSPINT136 in INTC
- The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Ic5121dd78c5dacf1ec4b4e791cc7bf476a8b608f
Link: https://lore.kernel.org/qemu-devel/20250313054020.2583556-7-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

show more ...


# 16677b0b 13-Mar-2025 Steven Lee <steven_lee@aspeedtech.com>

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC

AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:

- Introduce Aspeed2

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC

AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:

- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A0 SSP SoC
- Implement initialization and realization functions
- Add support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: If83e752873af393f3b71249176454399de0be40f
Link: https://lore.kernel.org/qemu-devel/20250313054020.2583556-6-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

show more ...


# d9e0888f 13-Mar-2025 Steven Lee <steven_lee@aspeedtech.com>

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC

The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:

- De

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC

The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:

- Defined IRQ maps for AST27x0 A1 SSP SoC
- Implemented initialization functions

The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt controller.

Difference from AST2700:

- AST2700
- Support GICINT128 to GICINT136 in INTC
- The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196

- AST2700-ssp
- Support SSPINT128 to SSPINT136 in INTC
- The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Ic5121dd78c5dacf1ec4b4e791cc7bf476a8b608f
Link: https://lore.kernel.org/qemu-devel/20250313054020.2583556-7-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

show more ...


# df3d1c26 13-Mar-2025 Steven Lee <steven_lee@aspeedtech.com>

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC

AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:

- Introduce Aspeed2

hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC

AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:

- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A0 SSP SoC
- Implement initialization and realization functions
- Add support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: If83e752873af393f3b71249176454399de0be40f
Link: https://lore.kernel.org/qemu-devel/20250313054020.2583556-6-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>

show more ...