| #
742b00b9 |
| 30-Jun-2022 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
PEL: Log spare clock failures as informational
This commit enables to log spare clock failure log as
informational.
For any sbe boot failures, application call pel api with
severity information. P
PEL: Log spare clock failures as informational
This commit enables to log spare clock failure log as
informational.
For any sbe boot failures, application call pel api with
severity information. PEL process the SBE FFDC information
and servicable information. For the spare clock failure
there is request from RAS team to log error as informational.
Tested: forced clock error on primary processor after bmc
clock isteps.
"User Header": {
"Section Version": "1",
"Sub-section type": "0",
"Log Committed by": "0x2000",
"Subsystem": "Processor Chip Cache",
"Event Scope": "Entire Platform",
"Event Severity": "Informational Event",
"Event Type": "Miscellaneous, Informational Only",
"Action Flags": [
"Service Action Required",
"Report Externally",
"HMC Call Home"
],
"Host Transmission": "Not Sent",
"HMC Transmission": "Not Sent"
},
"Primary SRC": {
"Section Version": "1",
"Sub-section type": "1",
"Created by": "0x3500",
"SRC Version": "0x02",
"SRC Format": "0x55",
"Virtual Progress SRC": "False",
"I5/OS Service Event Bit": "False",
"Hypervisor Dump Initiated":"False",
"Backplane CCIN": "2E33",
"Terminate FW Error": "False",
"Deconfigured": "False",
"Guarded": "False",
"Error Details": {
"Message": "Boot failure reported by SBE",
"SRC6": [
"0x0",
"[0:15] chip position"
]
},
"Valid Word Count": "0x09",
"Reference Code": "BD123503",
"Hex Word 2": "00080055",
"Hex Word 3": "2E330010",
"Hex Word 4": "00000000",
"Hex Word 5": "00000000",
"Hex Word 6": "00000000",
"Hex Word 7": "00000000",
"Hex Word 8": "00000000",
"Hex Word 9": "00000000",
"Callout Section": {
"Callout Count": "1",
"Callouts": [{
"FRU Type": "Symbolic FRU",
"Priority": "Mandatory, replace all with
this type as a unit",
"Part Number": "REFCLK0"
}]
}
},
"User Data 3": {
"Section Version": "1",
"Sub-section type": "1",
"Created by": "0x2000",
"Data": [
{
"Deconfigured": true,
"EntityPath": [
35,
1,
0,
2,
0,
26,
1,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
],
"Priority": "H",
"SymbolicFRU": "REFCLK0"
}
]
},
"User Data 4": {
"Section Version": "1",
"Sub-section type": "3",
"Created by": "0x2000",
"Data": [
"HWP_RC = RC_RCS_CLOCK_TEST_OUT_ERR",
"HWP_RC_DESC = xxxxxxx"
"HWP_FFDC_CLOCK_POS = 00",
"HWP_FFDC_READ_SNS1LTH = 00000000",
"HWP_FFDC_ATTR_CP_REFCLOCK_SELECT_VALUE = 02",
"HWP_FFDC_RCS_CLOCK_TEST_IN = 01",
"HWP_FFDC_CLOCK_A_OK = 00",
"HWP_FFDC_CLOCK_B_OK = 00",
"."
]
}
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I15cdd76237d4cdf52e9e6dc907528a66218354c1
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|
| #
0866c3fc |
| 07-Jun-2021 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
PEL: enable SBE FFDC support in pel log
FFDC Package structure and definitions are based on the
SBE chip-op spec.
FFDC packet Starts with a header word (Word 0) that has
an unique magic identifi
PEL: enable SBE FFDC support in pel log
FFDC Package structure and definitions are based on the
SBE chip-op spec.
FFDC packet Starts with a header word (Word 0) that has
an unique magic identifier code of 0xFFDC followed by the
length of the FFDC package including the header itself.
Word 1 contains a sequence id , command-class and command
fields. The sequence id field is ignored on the BMC side.
Word 2 contains a 32 bit Return Code which acts like the
key to the contents of subsequent FFDC Data Words (0-N).
A FFDC package can typically contain debug data from either:
1. A failed hardware procedure (e.g. local variable values
at point of failure) or
2. SBE firmware
(e.g. traces, attributes and other information).
___________________________________________________________
| | Byte 0 | Byte 1 | Byte 2 | Byte 3 |
|----------------------------------------------------------|
| Word 0 | Magic Bytes : 0xFFDC | Length in words (N+4) |
| Word 1 | [Sequence ID] | Command-Class | Command |
| Word 2 | Return Code 0..31 |
| Word 3 | FFDC Data – Word 0 |
| ... |
| Word N+3 | FFDC Data – Word N |
-----------------------------------------------------------
This commit enables SBE FFDC packet parsing for packet type
mentioned in option 1 (A failed hardware procedure). Other case
SBE provided tool based parsing is required. Not enabled in
this patch.
SBE FFDC file data added as part of PEL user data section for
future SBE tool based parsing.
Tested: Manually created SBE error with No core available for
Boot use case.
"User Data 2": { --> Raw SBE FFDC data
"Section Version": "1",
"Sub-section type": "203",
"Created by": "0x3500",
"Data": [
"FF DC 00 12 00 00 A1 01 00 8E CE 72 00 00 FF FE
"00 00 00 04 00 00 00 00 00 00 00 04 00 00 00 00
"00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 02
"00 00 00 04 00 00 00 00 00 00 00 00 00 00 00 04
"00 00 00 00 00 00 00 00
]
},
"User Data 3": { --> callout details
"Section Version": "1",
"Sub-section type": "1",
"Created by": "0x2000",
"Data": [
{
"Deconfigured": false,
"Guarded": false,
"LocationCode": "Ufcs-P0-C24",
"MRUs": [
{
"ID": 65536,
"Priority": "H"
}
],
"Priority": "H"
}
]
},
"User Data 4": { --> User Debug data.
"Section Version": "1",
"Sub-section type": "3",
"Created by": "0x2000",
"Data": [
"HWP_RC = RC_SBE_SELECT_EX_INSUFFICIENT_ACTIVE_CORES_ERROR",
"HWP_RC_DESC = The requested active cores were
not able to be configured.",
"HWP_FFDC_CHIP = 6b3a7570 306e3a30 3a30733a 00323070
00000000 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000 00000000",
"HWP_FFDC_CORE_CONFIG = 00000000",
"HWP_FFDC_ATTR_ACTIVE_CORES_NUM = 02",
"HWP_FFDC_ACTIVE_CORES_NUM = 00000000",
"HWP_FFDC_ACTIVE_CORES_VEC = 00000000",
"HWP_CDG_TGT_01_LOC_CODE = Ufcs-P0-C24",
"HWP_CDG_TGT_01_PHYS_PATH = physical:sys-0/node-0/proc-2",
"HWP_CDG_TGT_01_CO_REQ = true",
"HWP_CDG_TGT_01_CO_PRIORITY = HIGH",
"HWP_CDG_TGT_01_DECONF_REQ = false",
"HWP_CDG_TGT_01_GUARD_REQ = false",
"HWP_CDG_TGT_01_GUARD_TYPE = GARD_Fatal"
]
}
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: Id94d8e10b3e0f82cb61d40bab9ef8b3f4a3beff9
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| #
c74c2202 |
| 04-Jun-2021 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
PEL: Add SBE FFDC process function
Helper function to process SBE FFDC packet.
This function call libekb function to process the
FFDC packet and convert in to known format for PEL
specific file cre
PEL: Add SBE FFDC process function
Helper function to process SBE FFDC packet.
This function call libekb function to process the
FFDC packet and convert in to known format for PEL
specific file creation. This function also creates
json callout file and text type file, which includes
the addition debug data included in SBE FFDC packet.
Tested: Manually verified,
Sample test results with all the cores de-configured
system boot usecase.
"User Data 3": {
"Section Version": "1",
"Sub-section type": "1",
"Created by": "0x2000",
"Data": [
{
"Deconfigured": false,
"Guarded": false,
"LocationCode": "Ufcs-P0-C24",
"MRUs": [
{
"ID": 65536,
"Priority": "H"
}
],
"Priority": "H"
}
]
},
"User Data 4": {
"Section Version": "1",
"Sub-section type": "3",
"Created by": "0x2000",
"Data": [
"HWP_RC = RC_SBE_SELECT_EX_INSUFFICIENT_ACTIVE_CORES_ERROR",
"HWP_RC_DESC = The requested active cores were
not able to be configured.",
"HWP_FFDC_CHIP = 6b3a7570 306e3a30 3a30733a 00323070
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000",
"HWP_FFDC_CORE_CONFIG = 00000000",
"HWP_FFDC_ATTR_ACTIVE_CORES_NUM = 02",
"HWP_FFDC_ACTIVE_CORES_NUM = 00000000",
"HWP_FFDC_ACTIVE_CORES_VEC = 00000000",
"HWP_CDG_TGT_01_LOC_CODE = Ufcs-P0-C24",
"HWP_CDG_TGT_01_PHYS_PATH = physical:sys-0/node-0/proc-2",
"HWP_CDG_TGT_01_CO_REQ = true",
"HWP_CDG_TGT_01_CO_PRIORITY = HIGH",
"HWP_CDG_TGT_01_DECONF_REQ = false",
"HWP_CDG_TGT_01_GUARD_REQ = false",
"HWP_CDG_TGT_01_GUARD_TYPE = GARD_Fatal"
]
}
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: Iac2689c3608ddb0090a1c17753bbf9be96d12939
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| #
e8bdeeaa |
| 03-Jun-2021 |
Jayanth Othayoth <ojayanth@in.ibm.com> |
PEL: enable base infrastructure for SBE FFDC base PEL create
This commits provides the base infrastructure for SBE FFDC based
on createPELWithFFDCFiles`D-Bus method on the
org.open_power.Logging.PEL
PEL: enable base infrastructure for SBE FFDC base PEL create
This commits provides the base infrastructure for SBE FFDC based
on createPELWithFFDCFiles`D-Bus method on the
org.open_power.Logging.PEL.
More details related to usage of this interface is documented
as part of extensions/openpower-pels/README.md.
In the PEL create interface if the type is custom and subtype
is 0xCB, PEL class function invokes SBE FFDC function to process
SBE FFDC to extract Hardware procedure added user data section and
callouts. SBE FFDC class appends the callout json and create
user data file based FFDC information and continue the normal
PEL create function.
SCOPE of this commit:
- Add base infrastructure and control build only for "phal" supported
systems. "phal" feature is mandatory requirement for processing
SBE FFDC.
- Add SBE FFDC raw information in PEL user data section
To enable this feature use the below meson build options
meson build -Dopenpower-pel-extension=enabled -Dphal=enabled
Tested:
"Error Details": {
"Message":"chipop timeout reported during SBE communication",
"SRC6": [
"0x2",
"[0:15] chip position, [16:23] command class,
[24:31] command type"
]
},
"User Data 2": {
"Section Version": "1",
"Sub-section type": "203",
"Created by": "0x3500",
"Data": [
"FF DC 00 12 00 00 A1 01 00 8E CE 72 00 00 FF FE | ...........r....",
"00 00 00 04 00 00 00 00 00 00 00 04 00 00 00 00 | ................",
"00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 02 | ................",
"00 00 00 04 00 00 00 00 00 00 00 00 00 00 00 04 | ................",
"00 00 00 00 00 00 00 00 | ........"
]
}
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I2200b3ba9c0977be13e71f25e87f0b16cb50ec5b
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