PEL: Add the DRAM manufacturer info of DIMM callout in UD section

Add the called out DIMMs DRAM manufacturer info to the user data
section of the PEL to assist the service engineers in identifying t

PEL: Add the DRAM manufacturer info of DIMM callout in UD section

Add the called out DIMMs DRAM manufacturer info to the user data
section of the PEL to assist the service engineers in identifying the
manufacturer of the faulty DRAMs packaged within the DIMM module
directly from the logs, aiding in quick resolution.

The changes also moves the pdbg target and libekb initialization to
the PEL startup which avoids the need of multiple initialization as
the existing design.

When a PEL calls out a DIMM FRU, the DRAM manufacturer ID and the
expanded location code of those DIMMs are added to the SysInfo user
data section of the generated PEL in JSON format under the key 'DIMMs
Additional Info'.

In case of any errors occur during the collection or processing of
the manufacturer data, the error messages will be logged in the 'PEL
Internal Debug Data' section as a JSON array under the key 'DIMMs Info
Fetch Error' as a separate user data section.

Tested :

Below is a portion of PEL(callout section and User Data section are
shown) which callout the DIMM P0-C32.

```
"Hex Word 9": "00000000",
"Callout Section": {
"Callout Count": "1",
"Callouts": [{
"FRU Type": "Normal Hardware FRU",
"Priority": "Mandatory, replace all with this
type as a unit",
"Location Code": "UXXX.YYY.WWW004A-P0-C32",
"Part Number": "7777777",
"CCIN": "1234",
"Serial Number": "YYYYYY"
}]
}
```
"User Data": {
"Section Version": "1",
"Sub-section type": "1",
"Created by": "bmc error logging",
"BMCLoad": "0.65 0.69 0.64",
"BMCState": "Ready",
"BMCUptime": "0y 0d 0h 17m 43s",
"BootState": "Unspecified",
"ChassisState": "Off",
"DIMMs Additional Info": [
{
"DRAM Manufacturer ID": [
"0x88",
"0xAA"
]
"Location Code": "UXXX.YYY.WWW004A-P0-C32",
}
],
"FW Version ID": "fw1060.20-4-1060.2432.20240729a (NL1060_068)",
"HostState": "Off",
"System IM": "50001001"
}
```

Change-Id: I2ff81c66e63b99e8e84378ec78f586fb9b6322d7
Signed-off-by: Arya K Padman <aryakpadman@gmail.com>

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PEL: Changing the remaining traces to lg2 style

Some of the logging traces of PEL files still uses old style of logging.

Changing the remaining traces in PEL files to lg2 style of logging.Some
of t

PEL: Changing the remaining traces to lg2 style

Some of the logging traces of PEL files still uses old style of logging.

Changing the remaining traces in PEL files to lg2 style of logging.Some
of the traces in phosphor logging code which use the old style is also
considered.

Change-Id: I0daf9589af443881cb61730047c23db17fdec2c3
Signed-off-by: Arya K Padman <aryakpadman@gmail.com>

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PEL: Fix the max packets that can be received for Odyssey OCMB

There is no limit for the number of "ffdc" data packets that
can be received for Odyssey OCMB, a modified parser to loop
through the co

PEL: Fix the max packets that can be received for Odyssey OCMB

There is no limit for the number of "ffdc" data packets that
can be received for Odyssey OCMB, a modified parser to loop
through the complete data received in the ffdc file.

Now check the max ffdc packet count only for p10 proc ffdc.

Signed-off-by: Marri Devender Rao <devenrao@in.ibm.com>
Change-Id: I971490afd77d9558d52dbf3422b76239e73079b2

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PEL: Modify the sbe ffdc handler to cater for POZ format

A new format is defined for the FFDC data received from
odyssey SBE.

The old format will be used for the proc chip, and the new format will

PEL: Modify the sbe ffdc handler to cater for POZ format

A new format is defined for the FFDC data received from
odyssey SBE.

The old format will be used for the proc chip, and the new format will
be used for odyssey OCMB.

Using the chiptype defined in the additionalData section of the
PEL to collect the respective FFDC.

passing "chip type" to libekb to collect respective ffdc data.

Tested:
'''
---p10-poz format---
phosphor-log-manager[11319]: POZFFDC magic bytes 0xfbad
phosphor-log-manager[11319]: POZFFDC lengthinWords 0x18
phosphor-log-manager[11319]: POZFFDC seqId 0x0
phosphor-log-manager[11319]: POZFFDC cmdClass 0xc1
phosphor-log-manager[11319]: POZFFDC cmd 0x1
phosphor-log-manager[11319]: POZFFDC slid 0x2
phosphor-log-manager[11319]: POZFFDC severity 0x2
phosphor-log-manager[11319]: POZFFDC chipId 0x0
phosphor-log-manager[11319]: POZFFDC fapiRc 0x9fb509
phosphor-log-manager[11319]: POZFFDC pktLenWords 0x15

phosphor-log-manager[11319]: HWP_RC= RC_ERROR_UNSUPPORTED_BY_SBE
phosphor-log-manager[11319]: HWP_RC_DESC= An error was encountered
that the SBE didn't expect.
phosphor-log-manager[11319]: HWP_FFDC_INVALID_ERRVAL= 009fb509

---p10-ffdc format---
phosphor-log-manager[364]: SBE FFDC processing requested
phosphor-log-manager[364]: SBE FFDC file fd:(8), parsing started
phosphor-log-manager[364]: P10 FFDC magic: 65500 length in
words:151 Fapirc:81920
phosphor-log-manager[364]: P10 FFDC magic: 65500 length in
words:24 Fapirc:131584
phosphor-log-manager[364]: Created PEL 0x50005409 (BMC ID 842)
with SRC BD20F401
'''
Signed-off-by: Marri Devender Rao <devenrao@in.ibm.com>
Change-Id: Id6b1eb0e2b91c2459bf78abd52e6a3d233d81206

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PEL: Fix the memory leak error when parsing multiple ffdc packets

"ffdcData" array pointer of sbeFfdcPacketType is deleted as part
of the struct destructor

As the ffdcPkt is declared in the outer s

PEL: Fix the memory leak error when parsing multiple ffdc packets

"ffdcData" array pointer of sbeFfdcPacketType is deleted as part
of the struct destructor

As the ffdcPkt is declared in the outer scope, the memory allocated
gets released only once, and for multiple packets, there will be
memory leak

Change-Id: I2b224ea3db067d4086dbf3ab03ef65a21ae72b0e
Signed-off-by: Marri Devender Rao <devenrao@in.ibm.com>

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PEL: Move definitions and variables to the proper scope

Some of the variables and definitions defined in the header
file are used only in the implementation file, so moving those
to the implementati

PEL: Move definitions and variables to the proper scope

Some of the variables and definitions defined in the header
file are used only in the implementation file, so moving those
to the implementation file itself.

Tested:
No testing is required only need to pass compilation.

Change-Id: I4db72c12185b81c4e3e6dfa3f26d69081453c753
Signed-off-by: Marri Devender Rao <devenrao@in.ibm.com>

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PEL: switch fmt::format to use std::format

fmt::format is supported in the c++ std. This will
help to remove fmt package dependency.

Change-Id: I89f0a5b67bbfe54168a20e93c989a1ae87f54503
Signed-

PEL: switch fmt::format to use std::format

fmt::format is supported in the c++ std. This will
help to remove fmt package dependency.

Change-Id: I89f0a5b67bbfe54168a20e93c989a1ae87f54503
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>

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PEL: Close SBE FFDC file descriptors

The descriptors were being leaked since deleting the file doesn't close
the FD which was explicitly opened earlier.

Signed-off-by: Matt Spinler <spinler@us.ibm.

PEL: Close SBE FFDC file descriptors

The descriptors were being leaked since deleting the file doesn't close
the FD which was explicitly opened earlier.

Signed-off-by: Matt Spinler <spinler@us.ibm.com>
Change-Id: I5d0f1ed91f38af6830ea4f3c600adc402102564c

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clang-format: update with latest

Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Change-Id: I329396457b83bb2eb8740629b4ac1fbe9106bced

PEL: Fix more cppcheck warnings

This is the second of two commits to fix most of the cppcheck warnings
in the PEL code. It doesn't fix all of them because some are false
positives and some are just

PEL: Fix more cppcheck warnings

This is the second of two commits to fix most of the cppcheck warnings
in the PEL code. It doesn't fix all of them because some are false
positives and some are just suggestions.

It's broken up into two commits to make them smaller.

Signed-off-by: Matt Spinler <spinler@us.ibm.com>
Change-Id: Id9f462386df85fd25d09529d6b410115ff4ccba8

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PEL: Fix in getting processor position from SRC6

The value in the SRC6 is stored in the decimal form so
that string needs to be converted to integer first to get the
processor position from 0:15 bit

PEL: Fix in getting processor position from SRC6

The value in the SRC6 is stored in the decimal form so
that string needs to be converted to integer first to get the
processor position from 0:15 bits.

TESTS:
Executed the test to create PEL with SBE FFDC, there was
no crash.

Jun 23 06:30:46 p10bmc phosphor-log-manager[7794]: Created PEL 0x500010c9 (BMC ID 282) with SRC BD123500
Jun 23 06:30:46 p10bmc openpower-proc-control[17085]: exception raised
Jun 23 06:30:46 p10bmc openpower-proc-control[17085]: Enter: mpiplEnter(/proc2)
Jun 23 06:30:46 p10bmc openpower-proc-control[17085]: /proc2 CFAM(0x2986) : 0x2
Jun 23 06:30:46 p10bmc openpower-proc-control[17085]: /proc2 CFAM(0x2809) : 0x8366018F
Jun 23 06:30:46 p10bmc openpower-proc-control[17085]: /proc2 CFAM(0x282A) : 0x9A609A6
Jun 23 06:30:46 p10bmc openpower-proc-control[17085]: /proc2 CFAM(0x2829) : 0x99209A6
Jun 23 06:30:46 p10bmc openpower-proc-control[17085]: /proc2 CFAM(0x1007) : 0xC02083F8
Jun 23 06:30:46 p10bmc phosphor-log-manager[7794]: Created PEL 0x500010ca (BMC ID 283) with SRC BD123500
Jun 23 06:30:46 p10bmc openpower-proc-control[17086]: exception raised
Jun 23 06:30:46 p10bmc openpower-proc-control[17086]: Enter: mpiplEnter(/proc3)
Jun 23 06:30:46 p10bmc openpower-proc-control[17086]: /proc3 CFAM(0x2986) : 0x2
Jun 23 06:30:46 p10bmc openpower-proc-control[17086]: /proc3 CFAM(0x2809) : 0x8366018F
Jun 23 06:30:46 p10bmc openpower-proc-control[17086]: /proc3 CFAM(0x282A) : 0x9740960
Jun 23 06:30:46 p10bmc openpower-proc-control[17086]: /proc3 CFAM(0x2829) : 0x9560974
Jun 23 06:30:46 p10bmc openpower-proc-control[17086]: /proc3 CFAM(0x1007) : 0xC02083F8
Jun 23 06:30:46 p10bmc phosphor-log-manager[7794]: Created PEL 0x500010cb (BMC ID 284) with SRC BD123500
Jun 23 06:30:46 p10bmc openpower-proc-control[17083]: exception raised
Jun 23 06:30:46 p10bmc openpower-proc-control[17083]: Enter: mpiplEnter(/proc0)
Jun 23 06:30:46 p10bmc openpower-proc-control[17083]: /proc0 CFAM(0x2986) : 0x1
Jun 23 06:30:46 p10bmc openpower-proc-control[17083]: /proc0 CFAM(0x2809) : 0x8366018F
Jun 23 06:30:46 p10bmc openpower-proc-control[17083]: /proc0 CFAM(0x282A) : 0x9560942
Jun 23 06:30:46 p10bmc openpower-proc-control[17083]: /proc0 CFAM(0x2829) : 0x92E0974
Jun 23 06:30:46 p10bmc openpower-proc-control[17083]: /proc0 CFAM(0x1007) : 0xC02083F8
Jun 23 06:30:46 p10bmc openpower-proc-control[17070]: Memory preserving reboot failed
Jun 23 06:30:46 p10bmc phosphor-log-manager[7794]: Created PEL 0x500010cc (BMC ID 285) with SRC BD123500
Jun 23 06:30:46 p10bmc openpower-proc-control[17084]: exception raised
Jun 23 06:30:46 p10bmc openpower-proc-control[17084]: Enter: mpiplEnter(/proc1)
Jun 23 06:30:46 p10bmc openpower-proc-control[17084]: /proc1 CFAM(0x2986) : 0x2
Jun 23 06:30:46 p10bmc openpower-proc-control[17084]: /proc1 CFAM(0x2809) : 0x8366018F
Jun 23 06:30:46 p10bmc openpower-proc-control[17084]: /proc1 CFAM(0x282A) : 0x9B00988
Jun 23 06:30:46 p10bmc openpower-proc-control[17084]: /proc1 CFAM(0x2829) : 0x9880992
Jun 23 06:30:46 p10bmc openpower-proc-control[17084]: /proc1 CFAM(0x1007) : 0xC02083F8
Jun 23 06:30:46 p10bmc openpower-proc-control[17070]: Memory preserving reboot failed
Jun 23 06:30:46 p10bmc openpower-proc-control[17070]: Memory preserving reboot failed
Jun 23 06:30:46 p10bmc openpower-proc-control[17070]: Memory preserving reboot failed
Jun 23 06:30:46 p10bmc systemd[1]: op-enter-mpreboot@0.service: Main process exited, code=exited, status=1/FAILURE
Jun 23 06:30:46 p10bmc systemd[1]: op-enter-mpreboot@0.service: Failed with result 'exit-code'.
Jun 23 06:30:46 p10bmc systemd[1]: Failed to start Start memory preserving reboot host0.

Signed-off-by: Dhruvaraj Subhashchandran <dhruvaraj@in.ibm.com>
Change-Id: I2a1f6f7daebe9a01e00241c9f3587dd09f8668fb

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PEL: Log spare clock failures as informational

This commit enables to log spare clock failure log as
informational.

For any sbe boot failures, application call pel api with
severity information. P

PEL: Log spare clock failures as informational

This commit enables to log spare clock failure log as
informational.

For any sbe boot failures, application call pel api with
severity information. PEL process the SBE FFDC information
and servicable information. For the spare clock failure
there is request from RAS team to log error as informational.

Tested: forced clock error on primary processor after bmc
clock isteps.

"User Header": {
"Section Version": "1",
"Sub-section type": "0",
"Log Committed by": "0x2000",
"Subsystem": "Processor Chip Cache",
"Event Scope": "Entire Platform",
"Event Severity": "Informational Event",
"Event Type": "Miscellaneous, Informational Only",
"Action Flags": [
"Service Action Required",
"Report Externally",
"HMC Call Home"
],
"Host Transmission": "Not Sent",
"HMC Transmission": "Not Sent"
},
"Primary SRC": {
"Section Version": "1",
"Sub-section type": "1",
"Created by": "0x3500",
"SRC Version": "0x02",
"SRC Format": "0x55",
"Virtual Progress SRC": "False",
"I5/OS Service Event Bit": "False",
"Hypervisor Dump Initiated":"False",
"Backplane CCIN": "2E33",
"Terminate FW Error": "False",
"Deconfigured": "False",
"Guarded": "False",
"Error Details": {
"Message": "Boot failure reported by SBE",
"SRC6": [
"0x0",
"[0:15] chip position"
]
},
"Valid Word Count": "0x09",
"Reference Code": "BD123503",
"Hex Word 2": "00080055",
"Hex Word 3": "2E330010",
"Hex Word 4": "00000000",
"Hex Word 5": "00000000",
"Hex Word 6": "00000000",
"Hex Word 7": "00000000",
"Hex Word 8": "00000000",
"Hex Word 9": "00000000",
"Callout Section": {
"Callout Count": "1",
"Callouts": [{
"FRU Type": "Symbolic FRU",
"Priority": "Mandatory, replace all with
this type as a unit",
"Part Number": "REFCLK0"
}]
}
},
"User Data 3": {
"Section Version": "1",
"Sub-section type": "1",
"Created by": "0x2000",
"Data": [
{
"Deconfigured": true,
"EntityPath": [
35,
1,
0,
2,
0,
26,
1,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
],
"Priority": "H",
"SymbolicFRU": "REFCLK0"
}
]
},
"User Data 4": {
"Section Version": "1",
"Sub-section type": "3",
"Created by": "0x2000",
"Data": [
"HWP_RC = RC_RCS_CLOCK_TEST_OUT_ERR",
"HWP_RC_DESC = xxxxxxx"
"HWP_FFDC_CLOCK_POS = 00",
"HWP_FFDC_READ_SNS1LTH = 00000000",
"HWP_FFDC_ATTR_CP_REFCLOCK_SELECT_VALUE = 02",
"HWP_FFDC_RCS_CLOCK_TEST_IN = 01",
"HWP_FFDC_CLOCK_A_OK = 00",
"HWP_FFDC_CLOCK_B_OK = 00",
"."
]
}

Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I15cdd76237d4cdf52e9e6dc907528a66218354c1

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PEL: fix sbe ffdc packet offset calculation

Existing SBE ffdc packet offset calculation logic is wrong
and causing parser function failure for multiple packet
use-cases. Correct logic to calculate o

PEL: fix sbe ffdc packet offset calculation

Existing SBE ffdc packet offset calculation logic is wrong
and causing parser function failure for multiple packet
use-cases. Correct logic to calculate offset based on packet
sizen in bytes.

Tested: manually verified PEL log with two ffdc packet case.

Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: Ibc82fead1f49fdbf6510e2c704bc3561654aafed

show more ...

catch exceptions as const

Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Change-Id: Ic8e6ade739bd5ea6e79cac6b9bb2b182748e10c8

PEL: move libekb init function to sbe ffdc init

libekb init should run only after pdbg initialisation.

Tested: created sbe error and validated.

Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com

PEL: move libekb init function to sbe ffdc init

libekb init should run only after pdbg initialisation.

Tested: created sbe error and validated.

Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I8fe2b9ccff61e42aa0e6b0fd7bc6c85a295edd3e

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PEL: move pdbg init function to sbe ffdc init

BMC reboot followed by BMC software update pdbg attribute read
api failure due to pdbg default device tree selection instead
of BMC specific device tree

PEL: move pdbg init function to sbe ffdc init

BMC reboot followed by BMC software update pdbg attribute read
api failure due to pdbg default device tree selection instead
of BMC specific device tree. Pdbg initialises default
device tree incase user is not configured correctly.

In this usecase DEVTREE links initialises as part of
obmc-flash-bios-init.service, and this runs after
phosphor logging service. Proposed fix is to do pdbg
init as part of PEL request from application. This requests
only triggered when host

Tested: SBE PEL is created after software code update
and verified.

Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: Ie04d65b2d295d72c0ea9fe7b374dbb74a80d7a41

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PEL: enable SBE FFDC support in pel log

FFDC Package structure and definitions are based on the
SBE chip-op spec.
FFDC packet Starts with a header word (Word 0) that has
an unique magic identifi

PEL: enable SBE FFDC support in pel log

FFDC Package structure and definitions are based on the
SBE chip-op spec.
FFDC packet Starts with a header word (Word 0) that has
an unique magic identifier code of 0xFFDC followed by the
length of the FFDC package including the header itself.
Word 1 contains a sequence id , command-class and command
fields. The sequence id field is ignored on the BMC side.
Word 2 contains a 32 bit Return Code which acts like the
key to the contents of subsequent FFDC Data Words (0-N).

A FFDC package can typically contain debug data from either:
1. A failed hardware procedure (e.g. local variable values
at point of failure) or
2. SBE firmware
(e.g. traces, attributes and other information).
___________________________________________________________
| | Byte 0 | Byte 1 | Byte 2 | Byte 3 |
|----------------------------------------------------------|
| Word 0 | Magic Bytes : 0xFFDC | Length in words (N+4) |
| Word 1 | [Sequence ID] | Command-Class | Command |
| Word 2 | Return Code 0..31 |
| Word 3 | FFDC Data – Word 0 |
| ... |
| Word N+3 | FFDC Data – Word N |
-----------------------------------------------------------

This commit enables SBE FFDC packet parsing for packet type
mentioned in option 1 (A failed hardware procedure). Other case
SBE provided tool based parsing is required. Not enabled in
this patch.

SBE FFDC file data added as part of PEL user data section for
future SBE tool based parsing.

Tested: Manually created SBE error with No core available for
Boot use case.

"User Data 2": { --> Raw SBE FFDC data
"Section Version": "1",
"Sub-section type": "203",
"Created by": "0x3500",
"Data": [
"FF DC 00 12 00 00 A1 01 00 8E CE 72 00 00 FF FE
"00 00 00 04 00 00 00 00 00 00 00 04 00 00 00 00
"00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 02
"00 00 00 04 00 00 00 00 00 00 00 00 00 00 00 04
"00 00 00 00 00 00 00 00
]
},
"User Data 3": { --> callout details
"Section Version": "1",
"Sub-section type": "1",
"Created by": "0x2000",
"Data": [
{
"Deconfigured": false,
"Guarded": false,
"LocationCode": "Ufcs-P0-C24",
"MRUs": [
{
"ID": 65536,
"Priority": "H"
}
],
"Priority": "H"
}
]
},
"User Data 4": { --> User Debug data.
"Section Version": "1",
"Sub-section type": "3",
"Created by": "0x2000",
"Data": [
"HWP_RC = RC_SBE_SELECT_EX_INSUFFICIENT_ACTIVE_CORES_ERROR",
"HWP_RC_DESC = The requested active cores were
not able to be configured.",
"HWP_FFDC_CHIP = 6b3a7570 306e3a30 3a30733a 00323070
00000000 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000 00000000",
"HWP_FFDC_CORE_CONFIG = 00000000",
"HWP_FFDC_ATTR_ACTIVE_CORES_NUM = 02",
"HWP_FFDC_ACTIVE_CORES_NUM = 00000000",
"HWP_FFDC_ACTIVE_CORES_VEC = 00000000",
"HWP_CDG_TGT_01_LOC_CODE = Ufcs-P0-C24",
"HWP_CDG_TGT_01_PHYS_PATH = physical:sys-0/node-0/proc-2",
"HWP_CDG_TGT_01_CO_REQ = true",
"HWP_CDG_TGT_01_CO_PRIORITY = HIGH",
"HWP_CDG_TGT_01_DECONF_REQ = false",
"HWP_CDG_TGT_01_GUARD_REQ = false",
"HWP_CDG_TGT_01_GUARD_TYPE = GARD_Fatal"
]
}

Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: Id94d8e10b3e0f82cb61d40bab9ef8b3f4a3beff9

show more ...

PEL: Add SBE FFDC process function

Helper function to process SBE FFDC packet.
This function call libekb function to process the
FFDC packet and convert in to known format for PEL
specific file cre

PEL: Add SBE FFDC process function

Helper function to process SBE FFDC packet.
This function call libekb function to process the
FFDC packet and convert in to known format for PEL
specific file creation. This function also creates
json callout file and text type file, which includes
the addition debug data included in SBE FFDC packet.

Tested: Manually verified,

Sample test results with all the cores de-configured
system boot usecase.

"User Data 3": {
"Section Version": "1",
"Sub-section type": "1",
"Created by": "0x2000",
"Data": [
{
"Deconfigured": false,
"Guarded": false,
"LocationCode": "Ufcs-P0-C24",
"MRUs": [
{
"ID": 65536,
"Priority": "H"
}
],
"Priority": "H"
}
]
},
"User Data 4": {
"Section Version": "1",
"Sub-section type": "3",
"Created by": "0x2000",
"Data": [
"HWP_RC = RC_SBE_SELECT_EX_INSUFFICIENT_ACTIVE_CORES_ERROR",
"HWP_RC_DESC = The requested active cores were
not able to be configured.",
"HWP_FFDC_CHIP = 6b3a7570 306e3a30 3a30733a 00323070
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000",
"HWP_FFDC_CORE_CONFIG = 00000000",
"HWP_FFDC_ATTR_ACTIVE_CORES_NUM = 02",
"HWP_FFDC_ACTIVE_CORES_NUM = 00000000",
"HWP_FFDC_ACTIVE_CORES_VEC = 00000000",
"HWP_CDG_TGT_01_LOC_CODE = Ufcs-P0-C24",
"HWP_CDG_TGT_01_PHYS_PATH = physical:sys-0/node-0/proc-2",
"HWP_CDG_TGT_01_CO_REQ = true",
"HWP_CDG_TGT_01_CO_PRIORITY = HIGH",
"HWP_CDG_TGT_01_DECONF_REQ = false",
"HWP_CDG_TGT_01_GUARD_REQ = false",
"HWP_CDG_TGT_01_GUARD_TYPE = GARD_Fatal"
]
}

Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: Iac2689c3608ddb0090a1c17753bbf9be96d12939

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PEL: enable base infrastructure for SBE FFDC base PEL create

This commits provides the base infrastructure for SBE FFDC based
on createPELWithFFDCFiles`D-Bus method on the
org.open_power.Logging.PEL

PEL: enable base infrastructure for SBE FFDC base PEL create

This commits provides the base infrastructure for SBE FFDC based
on createPELWithFFDCFiles`D-Bus method on the
org.open_power.Logging.PEL.

More details related to usage of this interface is documented
as part of extensions/openpower-pels/README.md.

In the PEL create interface if the type is custom and subtype
is 0xCB, PEL class function invokes SBE FFDC function to process
SBE FFDC to extract Hardware procedure added user data section and
callouts. SBE FFDC class appends the callout json and create
user data file based FFDC information and continue the normal
PEL create function.

SCOPE of this commit:
- Add base infrastructure and control build only for "phal" supported
systems. "phal" feature is mandatory requirement for processing
SBE FFDC.
- Add SBE FFDC raw information in PEL user data section

To enable this feature use the below meson build options
meson build -Dopenpower-pel-extension=enabled -Dphal=enabled

Tested:

"Error Details": {
"Message":"chipop timeout reported during SBE communication",
"SRC6": [
"0x2",
"[0:15] chip position, [16:23] command class,
[24:31] command type"
]
},

"User Data 2": {
"Section Version": "1",
"Sub-section type": "203",
"Created by": "0x3500",
"Data": [
"FF DC 00 12 00 00 A1 01 00 8E CE 72 00 00 FF FE | ...........r....",
"00 00 00 04 00 00 00 00 00 00 00 04 00 00 00 00 | ................",
"00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 02 | ................",
"00 00 00 04 00 00 00 00 00 00 00 00 00 00 00 04 | ................",
"00 00 00 00 00 00 00 00 | ........"
]
}

Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I2200b3ba9c0977be13e71f25e87f0b16cb50ec5b

show more ...