2b2fe605 | 27-Jun-2023 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: Use rseq_unqual_scalar_typeof in macros
Use rseq_unqual_scalar_typeof() rather than typeof() in macros to remove the volatile qualifier (if there is one in the input argument), thus
selftests/rseq: Use rseq_unqual_scalar_typeof in macros
Use rseq_unqual_scalar_typeof() rather than typeof() in macros to remove the volatile qualifier (if there is one in the input argument), thus generating better assembly code in those scenarios.
Also add extra brackets around the "p" parameter in RSEQ_READ_ONCE(), RSEQ_WRITE_ONCE(), and rseq_unqual_scalar_typeof() across architectures to preserve expectations of operator priority. Here is an example that shows how operator priority may be an issue with missing parentheses:
#define m(p) \ do { \ __typeof__(*p) v = 0; \ } while (0)
void fct(unsigned long long *p1) { m(p1 + 1); /* works */ m(1 + p1); /* broken */ }
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Cc: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
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0fbbf07c | 27-Jun-2023 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: Fix arm64 buggy load-acquire/store-release macros
The arm64 load-acquire/store-release macros from the Linux kernel rseq selftests are buggy. Remplace them by a working implementatio
selftests/rseq: Fix arm64 buggy load-acquire/store-release macros
The arm64 load-acquire/store-release macros from the Linux kernel rseq selftests are buggy. Remplace them by a working implementation.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
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d6aaa23a | 27-Jun-2023 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: Implement rseq_unqual_scalar_typeof
Allow defining variables and perform cast with a typeof which removes the volatile and const qualifiers.
This prevents declaring a stack variable
selftests/rseq: Implement rseq_unqual_scalar_typeof
Allow defining variables and perform cast with a typeof which removes the volatile and const qualifiers.
This prevents declaring a stack variable with a volatile qualifier within a macro, which would generate sub-optimal assembler.
This is imported from the "librseq" project.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
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b344b8f2 | 16-Dec-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: Add mm_numa_cid to test script
Add mm_numa_cid tests to the run_param_test.sh test script.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zij
selftests/rseq: Add mm_numa_cid to test script
Add mm_numa_cid tests to the run_param_test.sh test script.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20221216145332.205095-1-mathieu.desnoyers@efficios.com
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a3798e6f | 22-Nov-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: parametrized test: Report/abort on negative concurrency ID
Report and abort when a negative concurrency ID value is observed by the spinlock test.
Signed-off-by: Mathieu Desnoyers <
selftests/rseq: parametrized test: Report/abort on negative concurrency ID
Report and abort when a negative concurrency ID value is observed by the spinlock test.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-21-mathieu.desnoyers@efficios.com
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ee31fff0 | 22-Nov-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: Implement parametrized mm_cid test
Adapt to the rseq.h API changes introduced by commits "selftests/rseq: <arch>: Template memory ordering and percpu access mode".
Build a new param
selftests/rseq: Implement parametrized mm_cid test
Adapt to the rseq.h API changes introduced by commits "selftests/rseq: <arch>: Template memory ordering and percpu access mode".
Build a new param_test_mm_cid, param_test_mm_cid_benchmark, and param_test_mm_cid_compare_twice executables to test the new "mm_cid" rseq field.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-20-mathieu.desnoyers@efficios.com
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cead7206 | 22-Nov-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: Implement basic percpu ops mm_cid test
Adapt to the rseq.h API changes introduced by commits "selftests/rseq: <arch>: Template memory ordering and percpu access mode".
Build a new b
selftests/rseq: Implement basic percpu ops mm_cid test
Adapt to the rseq.h API changes introduced by commits "selftests/rseq: <arch>: Template memory ordering and percpu access mode".
Build a new basic_percpu_ops_mm_cid_test to test the new "mm_cid" rseq field.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-19-mathieu.desnoyers@efficios.com
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171586a6 | 22-Nov-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: riscv: Template memory ordering and percpu access mode
Introduce a rseq-riscv-bits.h template header which is internally included to generate the static inline functions covering:
-
selftests/rseq: riscv: Template memory ordering and percpu access mode
Introduce a rseq-riscv-bits.h template header which is internally included to generate the static inline functions covering:
- relaxed and release memory ordering, - per-cpu-id and per-mm-cid per-cpu data access.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-18-mathieu.desnoyers@efficios.com
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a94af3c5 | 22-Nov-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: s390: Template memory ordering and percpu access mode
Introduce a rseq-s390-bits.h template header which is internally included to generate the static inline functions covering:
- r
selftests/rseq: s390: Template memory ordering and percpu access mode
Introduce a rseq-s390-bits.h template header which is internally included to generate the static inline functions covering:
- relaxed and release memory ordering, - per-cpu-id and per-mm-cid per-cpu data access.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-17-mathieu.desnoyers@efficios.com
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e61bd94c | 22-Nov-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: ppc: Template memory ordering and percpu access mode
Introduce a rseq-ppc-bits.h template header which is internally included to generate the static inline functions covering:
- rel
selftests/rseq: ppc: Template memory ordering and percpu access mode
Introduce a rseq-ppc-bits.h template header which is internally included to generate the static inline functions covering:
- relaxed and release memory ordering, - per-cpu-id and per-mm-cid per-cpu data access.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-16-mathieu.desnoyers@efficios.com
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431b6328 | 22-Nov-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: mips: Template memory ordering and percpu access mode
Introduce a rseq-mips-bits.h template header which is internally included to generate the static inline functions covering:
- r
selftests/rseq: mips: Template memory ordering and percpu access mode
Introduce a rseq-mips-bits.h template header which is internally included to generate the static inline functions covering:
- relaxed and release memory ordering, - per-cpu-id and per-mm-cid per-cpu data access.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-15-mathieu.desnoyers@efficios.com
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8d4eeb8b | 22-Nov-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: arm64: Template memory ordering and percpu access mode
Introduce a rseq-arm64-bits.h template header which is internally included to generate the static inline functions covering:
-
selftests/rseq: arm64: Template memory ordering and percpu access mode
Introduce a rseq-arm64-bits.h template header which is internally included to generate the static inline functions covering:
- relaxed and release memory ordering, - per-cpu-id and per-mm-cid per-cpu data access.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-14-mathieu.desnoyers@efficios.com
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5bf4aba3 | 22-Nov-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: arm: Template memory ordering and percpu access mode
Introduce a rseq-arm-bits.h template header which is internally included to generate the static inline functions covering:
- rel
selftests/rseq: arm: Template memory ordering and percpu access mode
Introduce a rseq-arm-bits.h template header which is internally included to generate the static inline functions covering:
- relaxed and release memory ordering, - per-cpu-id and per-mm-cid per-cpu data access.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-13-mathieu.desnoyers@efficios.com
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ae315738 | 22-Nov-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: x86: Template memory ordering and percpu access mode
Introduce a rseq-x86-bits.h template header which is internally included to generate the static inline functions covering:
- rel
selftests/rseq: x86: Template memory ordering and percpu access mode
Introduce a rseq-x86-bits.h template header which is internally included to generate the static inline functions covering:
- relaxed and release memory ordering, - per-cpu-id and per-mm-cid per-cpu data access.
This introduces changes to the rseq.h selftests API which require to update the rseq selftest programs. Similar API/templating changes need to be done for other architectures.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-12-mathieu.desnoyers@efficios.com
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18c23558 | 22-Nov-2022 |
Mathieu Desnoyers <mathieu.desnoyers@efficios.com> |
selftests/rseq: Implement rseq mm_cid field support
Add support for the mm_cid field (per-memory-map concurrency ID) of struct rseq to rseq selftests.
Signed-off-by: Mathieu Desnoyers <mathieu.desn
selftests/rseq: Implement rseq mm_cid field support
Add support for the mm_cid field (per-memory-map concurrency ID) of struct rseq to rseq selftests.
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221122203932.231377-11-mathieu.desnoyers@efficios.com
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