Merge branch 'next' into for-linus

Prepare input updates for 6.3 merge window.

Merge drm/drm-next into drm-misc-next

Backmerging into drm-misc-next to get DRM accelerator infrastructure,
which is required by ipuv driver.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

Merge wireless into wireless-next

Due to the two cherry picked commits from wireless to wireless-next we have
several conflicts in mt76. To avoid any bugs with conflicts merge wireless into
wireless

Merge wireless into wireless-next

Due to the two cherry picked commits from wireless to wireless-next we have
several conflicts in mt76. To avoid any bugs with conflicts merge wireless into
wireless-next.

96f134dc1964 wifi: mt76: handle possible mt76_rx_token_consume failures
fe13dad8992b wifi: mt76: dma: do not increment queue head if mt76_dma_add_buf fails

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Merge tag 'v6.2-rc3' into next

Merge with mainline to bring in timer_shutdown_sync() API.

Merge drm/drm-fixes into drm-misc-fixes

Let's start the fixes cycle.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>

Merge drm/drm-next into drm-intel-next

Sync up with v6.2-rc1.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Merge drm/drm-next into drm-intel-gt-next

Sync after v6.2-rc1 landed in drm-next.

We need to get some dependencies in place before we can merge
the fixes series from Gwan-gyeong and Chris.

Referen

Merge drm/drm-next into drm-intel-gt-next

Sync after v6.2-rc1 landed in drm-next.

We need to get some dependencies in place before we can merge
the fixes series from Gwan-gyeong and Chris.

References: https://lore.kernel.org/all/Y6x5JCDnh2rvh4lA@intel.com/
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

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Merge tag 'v6.2-rc1' into media_tree

Linux 6.2-rc1

* tag 'v6.2-rc1': (14398 commits)
Linux 6.2-rc1
treewide: Convert del_timer*() to timer_shutdown*()
pstore: Properly assign mem_type propert

Merge tag 'v6.2-rc1' into media_tree

Linux 6.2-rc1

* tag 'v6.2-rc1': (14398 commits)
Linux 6.2-rc1
treewide: Convert del_timer*() to timer_shutdown*()
pstore: Properly assign mem_type property
pstore: Make sure CONFIG_PSTORE_PMSG selects CONFIG_RT_MUTEXES
cfi: Fix CFI failure with KASAN
perf python: Fix splitting CC into compiler and options
afs: Stop implementing ->writepage()
afs: remove afs_cache_netfs and afs_zap_permits() declarations
afs: remove variable nr_servers
afs: Fix lost servers_outstanding count
ALSA: usb-audio: Add new quirk FIXED_RATE for JBL Quantum810 Wireless
ALSA: azt3328: Remove the unused function snd_azf3328_codec_outl()
gcov: add support for checksum field
test_maple_tree: add test for mas_spanning_rebalance() on insufficient data
maple_tree: fix mas_spanning_rebalance() on insufficient data
hugetlb: really allocate vma lock for all sharable vmas
kmsan: export kmsan_handle_urb
kmsan: include linux/vmalloc.h
mm/mempolicy: fix memory leak in set_mempolicy_home_node system call
mm, mremap: fix mremap() expanding vma with addr inside vma
...

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Merge remote-tracking branch 'torvalds/master' into perf/core

To resolve a trivial merge conflict with c302378bc157f6a7 ("libbpf:
Hashmap interface update to allow both long and void* keys/values"),

Merge remote-tracking branch 'torvalds/master' into perf/core

To resolve a trivial merge conflict with c302378bc157f6a7 ("libbpf:
Hashmap interface update to allow both long and void* keys/values"),
where a function present upstream was removed in the perf tools
development tree.

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

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Merge tags 'acpi-6.2-rc1' and 'irq-core-2022-12-10' into loongarch-next

LoongArch architecture changes for 6.2 depend on the acpi and irqchip
changes to work, so merge them to create a base.

Merge tag 'irq-core-2022-12-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq updates from Thomas Gleixner:
"Updates for the interrupt core and driver subsystem:

The bulk is

Merge tag 'irq-core-2022-12-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq updates from Thomas Gleixner:
"Updates for the interrupt core and driver subsystem:

The bulk is the rework of the MSI subsystem to support per device MSI
interrupt domains. This solves conceptual problems of the current
PCI/MSI design which are in the way of providing support for
PCI/MSI[-X] and the upcoming PCI/IMS mechanism on the same device.

IMS (Interrupt Message Store] is a new specification which allows
device manufactures to provide implementation defined storage for MSI
messages (as opposed to PCI/MSI and PCI/MSI-X that has a specified
message store which is uniform accross all devices). The PCI/MSI[-X]
uniformity allowed us to get away with "global" PCI/MSI domains.

IMS not only allows to overcome the size limitations of the MSI-X
table, but also gives the device manufacturer the freedom to store the
message in arbitrary places, even in host memory which is shared with
the device.

There have been several attempts to glue this into the current MSI
code, but after lengthy discussions it turned out that there is a
fundamental design problem in the current PCI/MSI-X implementation.
This needs some historical background.

When PCI/MSI[-X] support was added around 2003, interrupt management
was completely different from what we have today in the actively
developed architectures. Interrupt management was completely
architecture specific and while there were attempts to create common
infrastructure the commonalities were rudimentary and just providing
shared data structures and interfaces so that drivers could be written
in an architecture agnostic way.

The initial PCI/MSI[-X] support obviously plugged into this model
which resulted in some basic shared infrastructure in the PCI core
code for setting up MSI descriptors, which are a pure software
construct for holding data relevant for a particular MSI interrupt,
but the actual association to Linux interrupts was completely
architecture specific. This model is still supported today to keep
museum architectures and notorious stragglers alive.

In 2013 Intel tried to add support for hot-pluggable IO/APICs to the
kernel, which was creating yet another architecture specific mechanism
and resulted in an unholy mess on top of the existing horrors of x86
interrupt handling. The x86 interrupt management code was already an
incomprehensible maze of indirections between the CPU vector
management, interrupt remapping and the actual IO/APIC and PCI/MSI[-X]
implementation.

At roughly the same time ARM struggled with the ever growing SoC
specific extensions which were glued on top of the architected GIC
interrupt controller.

This resulted in a fundamental redesign of interrupt management and
provided the today prevailing concept of hierarchical interrupt
domains. This allowed to disentangle the interactions between x86
vector domain and interrupt remapping and also allowed ARM to handle
the zoo of SoC specific interrupt components in a sane way.

The concept of hierarchical interrupt domains aims to encapsulate the
functionality of particular IP blocks which are involved in interrupt
delivery so that they become extensible and pluggable. The X86
encapsulation looks like this:

|--- device 1
[Vector]---[Remapping]---[PCI/MSI]--|...
|--- device N

where the remapping domain is an optional component and in case that
it is not available the PCI/MSI[-X] domains have the vector domain as
their parent. This reduced the required interaction between the
domains pretty much to the initialization phase where it is obviously
required to establish the proper parent relation ship in the
components of the hierarchy.

While in most cases the model is strictly representing the chain of IP
blocks and abstracting them so they can be plugged together to form a
hierarchy, the design stopped short on PCI/MSI[-X]. Looking at the
hardware it's clear that the actual PCI/MSI[-X] interrupt controller
is not a global entity, but strict a per PCI device entity.

Here we took a short cut on the hierarchical model and went for the
easy solution of providing "global" PCI/MSI domains which was possible
because the PCI/MSI[-X] handling is uniform across the devices. This
also allowed to keep the existing PCI/MSI[-X] infrastructure mostly
unchanged which in turn made it simple to keep the existing
architecture specific management alive.

A similar problem was created in the ARM world with support for IP
block specific message storage. Instead of going all the way to stack
a IP block specific domain on top of the generic MSI domain this ended
in a construct which provides a "global" platform MSI domain which
allows overriding the irq_write_msi_msg() callback per allocation.

In course of the lengthy discussions we identified other abuse of the
MSI infrastructure in wireless drivers, NTB etc. where support for
implementation specific message storage was just mindlessly glued into
the existing infrastructure. Some of this just works by chance on
particular platforms but will fail in hard to diagnose ways when the
driver is used on platforms where the underlying MSI interrupt
management code does not expect the creative abuse.

Another shortcoming of today's PCI/MSI-X support is the inability to
allocate or free individual vectors after the initial enablement of
MSI-X. This results in an works by chance implementation of VFIO (PCI
pass-through) where interrupts on the host side are not set up upfront
to avoid resource exhaustion. They are expanded at run-time when the
guest actually tries to use them. The way how this is implemented is
that the host disables MSI-X and then re-enables it with a larger
number of vectors again. That works by chance because most device
drivers set up all interrupts before the device actually will utilize
them. But that's not universally true because some drivers allocate a
large enough number of vectors but do not utilize them until it's
actually required, e.g. for acceleration support. But at that point
other interrupts of the device might be in active use and the MSI-X
disable/enable dance can just result in losing interrupts and
therefore hard to diagnose subtle problems.

Last but not least the "global" PCI/MSI-X domain approach prevents to
utilize PCI/MSI[-X] and PCI/IMS on the same device due to the fact
that IMS is not longer providing a uniform storage and configuration
model.

The solution to this is to implement the missing step and switch from
global PCI/MSI domains to per device PCI/MSI domains. The resulting
hierarchy then looks like this:

|--- [PCI/MSI] device 1
[Vector]---[Remapping]---|...
|--- [PCI/MSI] device N

which in turn allows to provide support for multiple domains per
device:

|--- [PCI/MSI] device 1
|--- [PCI/IMS] device 1
[Vector]---[Remapping]---|...
|--- [PCI/MSI] device N
|--- [PCI/IMS] device N

This work converts the MSI and PCI/MSI core and the x86 interrupt
domains to the new model, provides new interfaces for post-enable
allocation/free of MSI-X interrupts and the base framework for
PCI/IMS. PCI/IMS has been verified with the work in progress IDXD
driver.

There is work in progress to convert ARM over which will replace the
platform MSI train-wreck. The cleanup of VFIO, NTB and other creative
"solutions" are in the works as well.

Drivers:

- Updates for the LoongArch interrupt chip drivers

- Support for MTK CIRQv2

- The usual small fixes and updates all over the place"

* tag 'irq-core-2022-12-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (134 commits)
irqchip/ti-sci-inta: Fix kernel doc
irqchip/gic-v2m: Mark a few functions __init
irqchip/gic-v2m: Include arm-gic-common.h
irqchip/irq-mvebu-icu: Fix works by chance pointer assignment
iommu/amd: Enable PCI/IMS
iommu/vt-d: Enable PCI/IMS
x86/apic/msi: Enable PCI/IMS
PCI/MSI: Provide pci_ims_alloc/free_irq()
PCI/MSI: Provide IMS (Interrupt Message Store) support
genirq/msi: Provide constants for PCI/IMS support
x86/apic/msi: Enable MSI_FLAG_PCI_MSIX_ALLOC_DYN
PCI/MSI: Provide post-enable dynamic allocation interfaces for MSI-X
PCI/MSI: Provide prepare_desc() MSI domain op
PCI/MSI: Split MSI-X descriptor setup
genirq/msi: Provide MSI_FLAG_MSIX_ALLOC_DYN
genirq/msi: Provide msi_domain_alloc_irq_at()
genirq/msi: Provide msi_domain_ops:: Prepare_desc()
genirq/msi: Provide msi_desc:: Msi_data
genirq/msi: Provide struct msi_map
x86/apic/msi: Remove arch_create_remap_msi_irq_domain()
...

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Merge tag 'irqchip-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates frim Marc Zyngier:

- More APCI fixes and improvements for the LoongArc

Merge tag 'irqchip-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates frim Marc Zyngier:

- More APCI fixes and improvements for the LoongArch architecture,
adding support for the HTVEC irqchip, suspend-resume, and some
PCI INTx workarounds

- Initial DT support for LoongArch. I'm not even kidding.

- Support for the MTK CIRQv2, a minor deviation from the original version

- Error handling fixes for wpcm450, GIC...

- BE detection for a FSL controller

- Declare the Sifive PLIC as wake-up agnostic

- Simplify fishing out the device data for the ST irqchip

- Mark some data structures as __initconst in the apple-aic driver

- Switch over from strtobool to kstrtobool

- COMPILE_TEST fixes

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Merge branch irq/loongarch-acpi into irq/irqchip-next

* irq/loongarch-acpi:
: .
: More APCI fixes and improvements for the LoongArch architecture:
:
: - Work around trigger type for INTx int

Merge branch irq/loongarch-acpi into irq/irqchip-next

* irq/loongarch-acpi:
: .
: More APCI fixes and improvements for the LoongArch architecture:
:
: - Work around trigger type for INTx interrupts described
: via ACPI (Jianmin Lv).
:
: - ACPI support got the HTVEC controller (Huacai Chen)
:
: - Suspend/resume across the board (Huacai Chen)
:
: - Fixes and random cleanups
: .
irqchip/loongarch: Adjust acpi_cascade_irqdomain_init() and sub-routines
irqchip/loongson-pch-lpc: Add suspend/resume support
irqchip/loongson-pch-pic: Add suspend/resume support
irqchip/loongson-eiointc: Add suspend/resume support
irqchip/loongson-htvec: Add suspend/resume support
irqchip/loongson-htvec: Add ACPI init support
irqchip/loongson-liointc: Support to set IRQ type for ACPI path
irqchip/loongson-pch-pic: Support to set IRQ type for ACPI path
irqchip/loongson-pch-pic: Fix translate callback for DT path
ACPI / PCI: fix LPIC IRQ model default PCI IRQ polarity

Signed-off-by: Marc Zyngier <maz@kernel.org>

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ACPI / PCI: fix LPIC IRQ model default PCI IRQ polarity

On LoongArch based systems, the PCI devices (e.g. SATA controllers and
PCI-to-PCI bridge controllers) in Loongson chipsets output high-level
i

ACPI / PCI: fix LPIC IRQ model default PCI IRQ polarity

On LoongArch based systems, the PCI devices (e.g. SATA controllers and
PCI-to-PCI bridge controllers) in Loongson chipsets output high-level
interrupt signal to the interrupt controller they are connected (see
Loongson 7A1000 Bridge User Manual v2.00, sec 5.3, "For the bridge chip,
AC97 DMA interrupts are edge triggered, gpio interrupts can be configured
to be level triggered or edge triggered as needed, and the rest of the
interrupts are level triggered and active high."), while the IRQs are
active low from the perspective of PCI (see Conventional PCI spec r3.0,
sec 2.2.6, "Interrupts on PCI are optional and defined as level sensitive,
asserted low."), which means that the interrupt output of PCI devices plugged
into PCI-to-PCI bridges of Loongson chipset will be also converted to high-level.
So high level triggered type is required to be passed to acpi_register_gsi()
when creating mappings for PCI devices.

Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20221022075955.11726-2-lvjianmin@loongson.cn

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Merge branch 'next' into for-linus

Prepare input updates for 5.15 merge window.

Merge tag 'v5.13' into next

Sync up with the mainline to get the latest parport API.

Merge tag 'v5.13-rc3' into asoc-5.13

Linux 5.13-rc3

Merge drm/drm-next into drm-intel-gt-next

Pulling in -rc2 fixes and TTM changes that next upcoming patches depend
on.

Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

Merge tag 'v5.13-rc2' into spi-5.13

Linux 5.13-rc2

Merge branch 'fixes-rc1' into fixes

Merge drm/drm-next into drm-intel-next

Time to get back in sync...

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Merge drm/drm-next into drm-misc-next

Backmerging to get v5.12 fixes. Requested for vmwgfx.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

Merge drm/drm-fixes into drm-misc-fixes

Start this new release drm-misc-fixes branch

Signed-off-by: Maxime Ripard <maxime@cerno.tech>

Merge tag 'acpi-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

Pull ACPI updates from Rafael Wysocki:
"These update the ACPICA code in the kernel to the most recent upst

Merge tag 'acpi-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

Pull ACPI updates from Rafael Wysocki:
"These update the ACPICA code in the kernel to the most recent upstream
revision including (but not limited to) new material introduced in the
6.4 version of the spec, update message printing in the ACPI-related
code, address a few issues and clean up code in a number of places.

Specifics:

- Update ACPICA code in the kernel to upstream revision 20210331
including the following changes:

* Add parsing for IVRS IVHD 40h and device entry F0h (Alexander
Monakov).

* Add new CEDT table for CXL 2.0 and iASL support for it (Ben
Widawsky, Bob Moore).

* NFIT: add Location Cookie field (Bob Moore).

* HMAT: add new fields/flags (Bob Moore).

* Add new flags in SRAT (Bob Moore).

* PMTT: add new fields/structures (Bob Moore).

* Add CSI2Bus resource template (Bob Moore).

* iASL: Decode subtable type field for VIOT (Bob Moore).

* Fix various typos and spelling mistakes (Colin Ian King).

* Add new predefined objects _BPC, _BPS, and _BPT (Erik Kaneda).

* Add USB4 capabilities UUID (Erik Kaneda).

* Add CXL ACPI device ID and _CBR object (Erik Kaneda).

* MADT: add Multiprocessor Wakeup Structure (Erik Kaneda).

* PCCT: add support for subtable type 5 (Erik Kaneda).

* PPTT: add new version of subtable type 1 (Erik Kaneda).

* Add SDEV secure access components (Erik Kaneda).

* Add support for PHAT table (Erik Kaneda).

* iASL: Add definitions for the VIOT table (Jean-Philippe
Brucker).

* acpisrc: Add missing conversion for VIOT support (Jean-Philippe
Brucker).

* IORT: Updates for revision E.b (Shameer Kolothum).

- Rearrange message printing in ACPI-related code to avoid using the
ACPICA's internal message printing macros outside ACPICA and do
some related code cleanups (Rafael Wysocki).

- Modify the device enumeration code to turn off all of the unused
ACPI power resources at the end (Rafael Wysocki).

- Change the ACPI power resources handling code to turn off unused
ACPI power resources without checking their status which should not
be necessary by the spec (Rafael Wysocki).

- Add empty stubs for CPPC-related functions to be used when
CONFIG_ACPI_CPPC_LIB is not set (Rafael Wysocki).

- Simplify device enumeration code (Rafael Wysocki).

- Change device enumeration code to use match_string() for string
matching (Andy Shevchenko).

- Modify irqresource_disabled() to retain the resouce flags that have
been set already (Angela Czubak).

- Add native backlight whitelist entry for GA401/GA502/GA503 (Luke
Jones).

- Modify the ACPI backlight driver to let the native backlight
handling take over on hardware-reduced systems (Hans de Goede).

- Introduce acpi_dev_get() and switch over the ACPI core code to
using it (Andy Shevchenko).

- Use kobj_attribute as callback argument instead of a local struct
type in the CPPC linrary code (Nathan Chancellor).

- Drop unneeded initializatio of a static variable from the ACPI
processor driver (Tian Tao).

- Drop unnecessary local variable assignment from the ACPI APEI code
(Colin Ian King).

- Document for_each_acpi_dev_match() macro (Andy Shevchenko).

- Address assorted coding style issues in multiple places (Xiaofei
Tan).

- Capitalize TLAs in a few comments (Andy Shevchenko).

- Correct assorted typos in comments (Tom Saeger)"

* tag 'acpi-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (68 commits)
ACPI: video: use native backlight for GA401/GA502/GA503
ACPI: APEI: remove redundant assignment to variable rc
ACPI: utils: Capitalize abbreviations in the comments
ACPI: utils: Document for_each_acpi_dev_match() macro
ACPI: bus: Introduce acpi_dev_get() and reuse it in ACPI code
ACPI: scan: Utilize match_string() API
resource: Prevent irqresource_disabled() from erasing flags
ACPI: CPPC: Replace cppc_attr with kobj_attribute
ACPI: scan: Call acpi_get_object_info() from acpi_set_pnp_ids()
ACPI: scan: Drop sta argument from acpi_init_device_object()
ACPI: scan: Drop sta argument from acpi_add_single_object()
ACPI: scan: Rearrange checks in acpi_bus_check_add()
ACPI: scan: Fold acpi_bus_type_and_status() into its caller
ACPI: video: Check LCD flag on ACPI-reduced-hardware devices
ACPI: utils: Add acpi_reduced_hardware() helper
ACPI: dock: fix some coding style issues
ACPI: sysfs: fix some coding style issues
ACPI: PM: add a missed blank line after declarations
ACPI: custom_method: fix a coding style issue
ACPI: CPPC: fix some coding style issues
...

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Merge branches 'acpi-pci' and 'acpi-processor'

* acpi-pci:
ACPI: PCI: Replace direct printk() invocations in pci_link.c
ACPI: PCI: Drop ACPI_PCI_COMPONENT that is not used any more
ACPI: PCI:

Merge branches 'acpi-pci' and 'acpi-processor'

* acpi-pci:
ACPI: PCI: Replace direct printk() invocations in pci_link.c
ACPI: PCI: Drop ACPI_PCI_COMPONENT that is not used any more
ACPI: PCI: Replace ACPI_DEBUG_PRINT() and ACPI_EXCEPTION()
ACPI: PCI: IRQ: Consolidate printing diagnostic messages

* acpi-processor:
ACPI: processor: perflib: Eliminate redundant status check
ACPI: processor: Get rid of ACPICA message printing
ACPI: processor: idle: Drop extra prefix from pr_notice()
ACPI: processor: Remove initialization of static variable

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