mmc.c (06ec045feeea08993834e2f1d2d1e4ec52cdeff1) mmc.c (8ac8a2630459bacb2d9b6516d49bedad61ca63f8)
1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */

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1098
1099static void mmc_set_bus_width(struct mmc *mmc, uint width)
1100{
1101 mmc->bus_width = width;
1102
1103 mmc_set_ios(mmc);
1104}
1105
1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */

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1098
1099static void mmc_set_bus_width(struct mmc *mmc, uint width)
1100{
1101 mmc->bus_width = width;
1102
1103 mmc_set_ios(mmc);
1104}
1105
1106static int sd_select_bus_freq_width(struct mmc *mmc)
1107{
1108 int err;
1109 struct mmc_cmd cmd;
1110
1111 err = sd_change_freq(mmc);
1112 if (err)
1113 return err;
1114
1115 /* Restrict card's capabilities by what the host can do */
1116 mmc->card_caps &= mmc->cfg->host_caps;
1117
1118 if (mmc->card_caps & MMC_MODE_4BIT) {
1119 cmd.cmdidx = MMC_CMD_APP_CMD;
1120 cmd.resp_type = MMC_RSP_R1;
1121 cmd.cmdarg = mmc->rca << 16;
1122
1123 err = mmc_send_cmd(mmc, &cmd, NULL);
1124 if (err)
1125 return err;
1126
1127 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1128 cmd.resp_type = MMC_RSP_R1;
1129 cmd.cmdarg = 2;
1130 err = mmc_send_cmd(mmc, &cmd, NULL);
1131 if (err)
1132 return err;
1133
1134 mmc_set_bus_width(mmc, 4);
1135 }
1136
1137 err = sd_read_ssr(mmc);
1138 if (err)
1139 return err;
1140
1141 if (mmc->card_caps & MMC_MODE_HS)
1142 mmc->tran_speed = 50000000;
1143 else
1144 mmc->tran_speed = 25000000;
1145
1146 return 0;
1147}
1148
1149static int mmc_select_bus_freq_width(struct mmc *mmc, const u8 *ext_csd)
1150{
1151 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1152 /* An array of possible bus widths in order of preference */
1153 static const unsigned int ext_csd_bits[] = {
1154 EXT_CSD_DDR_BUS_WIDTH_8,
1155 EXT_CSD_DDR_BUS_WIDTH_4,
1156 EXT_CSD_BUS_WIDTH_8,
1157 EXT_CSD_BUS_WIDTH_4,
1158 EXT_CSD_BUS_WIDTH_1,
1159 };
1160 /* An array to map CSD bus widths to host cap bits */
1161 static const unsigned int ext_to_hostcaps[] = {
1162 [EXT_CSD_DDR_BUS_WIDTH_4] =
1163 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1164 [EXT_CSD_DDR_BUS_WIDTH_8] =
1165 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1166 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1167 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1168 };
1169 /* An array to map chosen bus width to an integer */
1170 static const unsigned int widths[] = {
1171 8, 4, 8, 4, 1,
1172 };
1173 int err;
1174 int idx;
1175
1176 err = mmc_change_freq(mmc);
1177 if (err)
1178 return err;
1179
1180 /* Restrict card's capabilities by what the host can do */
1181 mmc->card_caps &= mmc->cfg->host_caps;
1182
1183 /* Only version 4 of MMC supports wider bus widths */
1184 if (mmc->version < MMC_VERSION_4)
1185 return 0;
1186
1187 for (idx = 0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1188 unsigned int extw = ext_csd_bits[idx];
1189 unsigned int caps = ext_to_hostcaps[extw];
1190 /*
1191 * If the bus width is still not changed,
1192 * don't try to set the default again.
1193 * Otherwise, recover from switch attempts
1194 * by switching to 1-bit bus width.
1195 */
1196 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1197 mmc->bus_width == 1) {
1198 err = 0;
1199 break;
1200 }
1201
1202 /*
1203 * Check to make sure the card and controller support
1204 * these capabilities
1205 */
1206 if ((mmc->card_caps & caps) != caps)
1207 continue;
1208
1209 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1210 EXT_CSD_BUS_WIDTH, extw);
1211
1212 if (err)
1213 continue;
1214
1215 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1216 mmc_set_bus_width(mmc, widths[idx]);
1217
1218 err = mmc_send_ext_csd(mmc, test_csd);
1219
1220 if (err)
1221 continue;
1222
1223 /* Only compare read only fields */
1224 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1225 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1226 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1227 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1228 ext_csd[EXT_CSD_REV]
1229 == test_csd[EXT_CSD_REV] &&
1230 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1231 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1232 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1233 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1234 break;
1235
1236 err = -EBADMSG;
1237 }
1238
1239 if (err)
1240 return err;
1241
1242 if (mmc->card_caps & MMC_MODE_HS) {
1243 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1244 mmc->tran_speed = 52000000;
1245 else
1246 mmc->tran_speed = 26000000;
1247 }
1248
1249 return err;
1250}
1251
1106static int mmc_startup(struct mmc *mmc)
1107{
1108 int err, i;
1109 uint mult, freq;
1110 u64 cmult, csize, capacity;
1111 struct mmc_cmd cmd;
1112 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1252static int mmc_startup(struct mmc *mmc)
1253{
1254 int err, i;
1255 uint mult, freq;
1256 u64 cmult, csize, capacity;
1257 struct mmc_cmd cmd;
1258 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1113 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1114 bool has_parts = false;
1115 bool part_completed;
1116 struct blk_desc *bdesc;
1117
1118#ifdef CONFIG_MMC_SPI_CRC_ON
1119 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1120 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1121 cmd.resp_type = MMC_RSP_R1;

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1410 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1411 }
1412
1413 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1414 if (err)
1415 return err;
1416
1417 if (IS_SD(mmc))
1259 bool has_parts = false;
1260 bool part_completed;
1261 struct blk_desc *bdesc;
1262
1263#ifdef CONFIG_MMC_SPI_CRC_ON
1264 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1265 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1266 cmd.resp_type = MMC_RSP_R1;

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1555 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1556 }
1557
1558 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1559 if (err)
1560 return err;
1561
1562 if (IS_SD(mmc))
1418 err = sd_change_freq(mmc);
1563 err = sd_select_bus_freq_width(mmc);
1419 else
1564 else
1420 err = mmc_change_freq(mmc);
1565 err = mmc_select_bus_freq_width(mmc, ext_csd);
1421
1422 if (err)
1423 return err;
1424
1566
1567 if (err)
1568 return err;
1569
1425 /* Restrict card's capabilities by what the host can do */
1426 mmc->card_caps &= mmc->cfg->host_caps;
1427
1428 if (IS_SD(mmc)) {
1429 if (mmc->card_caps & MMC_MODE_4BIT) {
1430 cmd.cmdidx = MMC_CMD_APP_CMD;
1431 cmd.resp_type = MMC_RSP_R1;
1432 cmd.cmdarg = mmc->rca << 16;
1433
1434 err = mmc_send_cmd(mmc, &cmd, NULL);
1435 if (err)
1436 return err;
1437
1438 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1439 cmd.resp_type = MMC_RSP_R1;
1440 cmd.cmdarg = 2;
1441 err = mmc_send_cmd(mmc, &cmd, NULL);
1442 if (err)
1443 return err;
1444
1445 mmc_set_bus_width(mmc, 4);
1446 }
1447
1448 err = sd_read_ssr(mmc);
1449 if (err)
1450 return err;
1451
1452 if (mmc->card_caps & MMC_MODE_HS)
1453 mmc->tran_speed = 50000000;
1454 else
1455 mmc->tran_speed = 25000000;
1456 } else if (mmc->version >= MMC_VERSION_4) {
1457 /* Only version 4 of MMC supports wider bus widths */
1458 int idx;
1459
1460 /* An array of possible bus widths in order of preference */
1461 static unsigned ext_csd_bits[] = {
1462 EXT_CSD_DDR_BUS_WIDTH_8,
1463 EXT_CSD_DDR_BUS_WIDTH_4,
1464 EXT_CSD_BUS_WIDTH_8,
1465 EXT_CSD_BUS_WIDTH_4,
1466 EXT_CSD_BUS_WIDTH_1,
1467 };
1468
1469 /* An array to map CSD bus widths to host cap bits */
1470 static unsigned ext_to_hostcaps[] = {
1471 [EXT_CSD_DDR_BUS_WIDTH_4] =
1472 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1473 [EXT_CSD_DDR_BUS_WIDTH_8] =
1474 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1475 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1476 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1477 };
1478
1479 /* An array to map chosen bus width to an integer */
1480 static unsigned widths[] = {
1481 8, 4, 8, 4, 1,
1482 };
1483
1484 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1485 unsigned int extw = ext_csd_bits[idx];
1486 unsigned int caps = ext_to_hostcaps[extw];
1487
1488 /*
1489 * If the bus width is still not changed,
1490 * don't try to set the default again.
1491 * Otherwise, recover from switch attempts
1492 * by switching to 1-bit bus width.
1493 */
1494 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1495 mmc->bus_width == 1) {
1496 err = 0;
1497 break;
1498 }
1499
1500 /*
1501 * Check to make sure the card and controller support
1502 * these capabilities
1503 */
1504 if ((mmc->card_caps & caps) != caps)
1505 continue;
1506
1507 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1508 EXT_CSD_BUS_WIDTH, extw);
1509
1510 if (err)
1511 continue;
1512
1513 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1514 mmc_set_bus_width(mmc, widths[idx]);
1515
1516 err = mmc_send_ext_csd(mmc, test_csd);
1517
1518 if (err)
1519 continue;
1520
1521 /* Only compare read only fields */
1522 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1523 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1524 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1525 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1526 ext_csd[EXT_CSD_REV]
1527 == test_csd[EXT_CSD_REV] &&
1528 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1529 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1530 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1531 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1532 break;
1533 else
1534 err = -EBADMSG;
1535 }
1536
1537 if (err)
1538 return err;
1539
1540 if (mmc->card_caps & MMC_MODE_HS) {
1541 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1542 mmc->tran_speed = 52000000;
1543 else
1544 mmc->tran_speed = 26000000;
1545 }
1546 }
1547
1548 mmc_set_clock(mmc, mmc->tran_speed);
1549
1550 /* Fix the block length for DDR mode */
1551 if (mmc->ddr_mode) {
1552 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1553 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1554 }
1555

--- 336 unchanged lines hidden --- 		1570 mmc_set_clock(mmc, mmc->tran_speed);
1571
1572 /* Fix the block length for DDR mode */
1573 if (mmc->ddr_mode) {
1574 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1575 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1576 }
1577

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