zynqpl.c (5b30997fd26f0e13837e9ba3cd289a037b8353bd) zynqpl.c (71723aaec5e6dbfbc401d65461fe1cae98912e79)
1/*
2 * (C) Copyright 2012-2013, Xilinx, Michal Simek
3 *
4 * (C) Copyright 2012
5 * Joe Hershberger <joe.hershberger@ni.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <console.h>
12#include <asm/io.h>
13#include <fs.h>
14#include <zynqpl.h>
15#include <linux/sizes.h>
16#include <asm/arch/hardware.h>
17#include <asm/arch/sys_proto.h>
18
19#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
1/*
2 * (C) Copyright 2012-2013, Xilinx, Michal Simek
3 *
4 * (C) Copyright 2012
5 * Joe Hershberger <joe.hershberger@ni.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <console.h>
12#include <asm/io.h>
13#include <fs.h>
14#include <zynqpl.h>
15#include <linux/sizes.h>
16#include <asm/arch/hardware.h>
17#include <asm/arch/sys_proto.h>
18
19#define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
20#define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
20#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
21#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
22#define DEVCFG_ISR_RX_FIFO_OV 0x00040000
23#define DEVCFG_ISR_DMA_DONE 0x00002000
24#define DEVCFG_ISR_PCFG_DONE 0x00000004
25#define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
26#define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
27#define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000

--- 172 unchanged lines hidden (view full) ---

200 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
201
202 if (bstype != BIT_PARTIAL) {
203 zynq_slcr_devcfg_disable();
204
205 /* Setting PCFG_PROG_B signal to high */
206 control = readl(&devcfg_base->ctrl);
207 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
21#define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
22#define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
23#define DEVCFG_ISR_RX_FIFO_OV 0x00040000
24#define DEVCFG_ISR_DMA_DONE 0x00002000
25#define DEVCFG_ISR_PCFG_DONE 0x00000004
26#define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
27#define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
28#define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000

--- 172 unchanged lines hidden (view full) ---

201 clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
202
203 if (bstype != BIT_PARTIAL) {
204 zynq_slcr_devcfg_disable();
205
206 /* Setting PCFG_PROG_B signal to high */
207 control = readl(&devcfg_base->ctrl);
208 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
209
210 /*
211 * Delay is required if AES efuse is selected as
212 * key source.
213 */
214 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
215 mdelay(5);
216
208 /* Setting PCFG_PROG_B signal to low */
209 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
210
217 /* Setting PCFG_PROG_B signal to low */
218 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
219
220 /*
221 * Delay is required if AES efuse is selected as
222 * key source.
223 */
224 if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
225 mdelay(5);
226
211 /* Polling the PCAP_INIT status for Reset */
212 ts = get_timer(0);
213 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
214 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
215 printf("%s: Timeout wait for INIT to clear\n",
216 __func__);
217 return FPGA_FAIL;
218 }

--- 266 unchanged lines hidden --- 		227 /* Polling the PCAP_INIT status for Reset */
228 ts = get_timer(0);
229 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
230 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
231 printf("%s: Timeout wait for INIT to clear\n",
232 __func__);
233 return FPGA_FAIL;
234 }

--- 266 unchanged lines hidden ---