options.c (1ad6364eeb4f578e423081d1748e8a3fdf1ab01d) options.c (34e026f9b1eb3bcffb38e7787c2e6eac0e88ba85)
1/*
1/*
2 * Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
2 * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <hwconfig.h>
9#include <fsl_ddr_sdram.h>
10

--- 13 unchanged lines hidden (view full) ---

24
25struct dynamic_odt {
26 unsigned int odt_rd_cfg;
27 unsigned int odt_wr_cfg;
28 unsigned int odt_rtt_norm;
29 unsigned int odt_rtt_wr;
30};
31
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <hwconfig.h>
9#include <fsl_ddr_sdram.h>
10

--- 13 unchanged lines hidden (view full) ---

24
25struct dynamic_odt {
26 unsigned int odt_rd_cfg;
27 unsigned int odt_wr_cfg;
28 unsigned int odt_rtt_norm;
29 unsigned int odt_rtt_wr;
30};
31
32#ifdef CONFIG_SYS_FSL_DDR3
32#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
33static const struct dynamic_odt single_Q[4] = {
34 { /* cs0 */
35 FSL_DDR_ODT_NEVER,
36 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
37 DDR3_RTT_20_OHM,
38 DDR3_RTT_120_OHM
39 },
40 { /* cs1 */

--- 213 unchanged lines hidden (view full) ---

254 },
255 { /* cs3 */
256 FSL_DDR_ODT_NEVER,
257 FSL_DDR_ODT_CS,
258 DDR3_RTT_120_OHM,
259 DDR3_RTT_OFF
260 }
261};
33static const struct dynamic_odt single_Q[4] = {
34 { /* cs0 */
35 FSL_DDR_ODT_NEVER,
36 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
37 DDR3_RTT_20_OHM,
38 DDR3_RTT_120_OHM
39 },
40 { /* cs1 */

--- 213 unchanged lines hidden (view full) ---

254 },
255 { /* cs3 */
256 FSL_DDR_ODT_NEVER,
257 FSL_DDR_ODT_CS,
258 DDR3_RTT_120_OHM,
259 DDR3_RTT_OFF
260 }
261};
262#else /* CONFIG_SYS_FSL_DDR3 */
262#else /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */
263static const struct dynamic_odt single_Q[4] = {
264 {0, 0, 0, 0},
265 {0, 0, 0, 0},
266 {0, 0, 0, 0},
267 {0, 0, 0, 0}
268};
269
270static const struct dynamic_odt single_D[4] = {

--- 231 unchanged lines hidden (view full) ---

502unsigned int populate_memctl_options(int all_dimms_registered,
503 memctl_options_t *popts,
504 dimm_params_t *pdimm,
505 unsigned int ctrl_num)
506{
507 unsigned int i;
508 char buffer[HWCONFIG_BUFFER_SIZE];
509 char *buf = NULL;
263static const struct dynamic_odt single_Q[4] = {
264 {0, 0, 0, 0},
265 {0, 0, 0, 0},
266 {0, 0, 0, 0},
267 {0, 0, 0, 0}
268};
269
270static const struct dynamic_odt single_D[4] = {

--- 231 unchanged lines hidden (view full) ---

502unsigned int populate_memctl_options(int all_dimms_registered,
503 memctl_options_t *popts,
504 dimm_params_t *pdimm,
505 unsigned int ctrl_num)
506{
507 unsigned int i;
508 char buffer[HWCONFIG_BUFFER_SIZE];
509 char *buf = NULL;
510#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
510#if defined(CONFIG_SYS_FSL_DDR3) || \
511 defined(CONFIG_SYS_FSL_DDR2) || \
512 defined(CONFIG_SYS_FSL_DDR4)
511 const struct dynamic_odt *pdodt = odt_unknown;
512#endif
513 ulong ddr_freq;
514
515 /*
516 * Extract hwconfig from environment since we have not properly setup
517 * the environment but need it for ddr config params
518 */
519 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
520 buf = buffer;
521
513 const struct dynamic_odt *pdodt = odt_unknown;
514#endif
515 ulong ddr_freq;
516
517 /*
518 * Extract hwconfig from environment since we have not properly setup
519 * the environment but need it for ddr config params
520 */
521 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
522 buf = buffer;
523
522#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
524#if defined(CONFIG_SYS_FSL_DDR3) || \
525 defined(CONFIG_SYS_FSL_DDR2) || \
526 defined(CONFIG_SYS_FSL_DDR4)
523 /* Chip select options. */
524 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
525 switch (pdimm[0].n_ranks) {
526 case 1:
527 pdodt = single_S;
528 break;
529 case 2:
530 pdodt = single_D;

--- 49 unchanged lines hidden (view full) ---

580 }
581 break;
582 }
583 }
584#endif
585
586 /* Pick chip-select local options. */
587 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
527 /* Chip select options. */
528 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
529 switch (pdimm[0].n_ranks) {
530 case 1:
531 pdodt = single_S;
532 break;
533 case 2:
534 pdodt = single_D;

--- 49 unchanged lines hidden (view full) ---

584 }
585 break;
586 }
587 }
588#endif
589
590 /* Pick chip-select local options. */
591 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
588#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR2)
592#if defined(CONFIG_SYS_FSL_DDR3) || \
593 defined(CONFIG_SYS_FSL_DDR2) || \
594 defined(CONFIG_SYS_FSL_DDR4)
589 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
590 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
591 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
592 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
593#else
594 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
595 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
596#endif

--- 101 unchanged lines hidden (view full) ---

698 pdimm[0].primary_sdram_width);
699 }
700 }
701#endif
702
703 popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
704
705 /* Choose burst length. */
595 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
596 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
597 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
598 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
599#else
600 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
601 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
602#endif

--- 101 unchanged lines hidden (view full) ---

704 pdimm[0].primary_sdram_width);
705 }
706 }
707#endif
708
709 popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
710
711 /* Choose burst length. */
706#if defined(CONFIG_SYS_FSL_DDR3)
712#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
707#if defined(CONFIG_E500MC)
708 popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
709 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
710#else
711 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
712 /* 32-bit or 16-bit bus */
713 popts->otf_burst_chop_en = 0;
714 popts->burst_length = DDR_BL8;
715 } else {
716 popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */
717 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
718 }
719#endif
720#else
721 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
722#endif
723
724 /* Choose ddr controller address mirror mode */
713#if defined(CONFIG_E500MC)
714 popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
715 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
716#else
717 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
718 /* 32-bit or 16-bit bus */
719 popts->otf_burst_chop_en = 0;
720 popts->burst_length = DDR_BL8;
721 } else {
722 popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */
723 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
724 }
725#endif
726#else
727 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
728#endif
729
730 /* Choose ddr controller address mirror mode */
725#if defined(CONFIG_SYS_FSL_DDR3)
731#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
726 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
727#endif
728
729 /* Global Timing Parameters. */
730 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
731
732 /* Pick a caslat override. */
733 popts->cas_latency_override = 0;

--- 27 unchanged lines hidden (view full) ---

761
762 /* for RDIMM, address parity enable */
763 popts->ap_en = 1;
764
765 /*
766 * BSTTOPRE precharge interval
767 *
768 * Set this to 0 for global auto precharge
732 popts->mirrored_dimm = pdimm[0].mirrored_dimm;
733#endif
734
735 /* Global Timing Parameters. */
736 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
737
738 /* Pick a caslat override. */
739 popts->cas_latency_override = 0;

--- 27 unchanged lines hidden (view full) ---

767
768 /* for RDIMM, address parity enable */
769 popts->ap_en = 1;
770
771 /*
772 * BSTTOPRE precharge interval
773 *
774 * Set this to 0 for global auto precharge
769 *
770 * FIXME: Should this be configured in picoseconds?
771 * Why it should be in ps: better understanding of this
772 * relative to actual DRAM timing parameters such as tRAS.
773 * e.g. tRAS(min) = 40 ns
775 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
776 * It is not wrong. Any value should be OK. The performance depends on
777 * applications. There is no one good value for all.
774 */
775 popts->bstopre = 0x100;
776
777 /* Minimum CKE pulse width -- tCKE(MIN) */
778 popts->tcke_clock_pulse_width_ps
779 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
780
781 /*

--- 8 unchanged lines hidden (view full) ---

790
791#elif defined(CONFIG_SYS_FSL_DDR2)
792 /*
793 * x4/x8; some datasheets have 35000
794 * x16 wide columns only? Use 50000?
795 */
796 popts->tfaw_window_four_activates_ps = 37500;
797
778 */
779 popts->bstopre = 0x100;
780
781 /* Minimum CKE pulse width -- tCKE(MIN) */
782 popts->tcke_clock_pulse_width_ps
783 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
784
785 /*

--- 8 unchanged lines hidden (view full) ---

794
795#elif defined(CONFIG_SYS_FSL_DDR2)
796 /*
797 * x4/x8; some datasheets have 35000
798 * x16 wide columns only? Use 50000?
799 */
800 popts->tfaw_window_four_activates_ps = 37500;
801
798#elif defined(CONFIG_SYS_FSL_DDR3)
802#else
799 popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
800#endif
801 popts->zq_en = 0;
802 popts->wrlvl_en = 0;
803 popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
804#endif
805 popts->zq_en = 0;
806 popts->wrlvl_en = 0;
803#if defined(CONFIG_SYS_FSL_DDR3)
807#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
804 /*
805 * due to ddr3 dimm is fly-by topology
806 * we suggest to enable write leveling to
807 * meet the tQDSS under different loading.
808 */
809 popts->wrlvl_en = 1;
810 popts->zq_en = 1;
811 popts->wrlvl_override = 0;

--- 349 unchanged lines hidden --- 		808 /*
809 * due to ddr3 dimm is fly-by topology
810 * we suggest to enable write leveling to
811 * meet the tQDSS under different loading.
812 */
813 popts->wrlvl_en = 1;
814 popts->zq_en = 1;
815 popts->wrlvl_override = 0;

--- 349 unchanged lines hidden ---