1 /* 2 * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <hwconfig.h> 9 #include <fsl_ddr_sdram.h> 10 11 #include <fsl_ddr.h> 12 13 /* 14 * Use our own stack based buffer before relocation to allow accessing longer 15 * hwconfig strings that might be in the environment before we've relocated. 16 * This is pretty fragile on both the use of stack and if the buffer is big 17 * enough. However we will get a warning from getenv_f for the later. 18 */ 19 20 /* Board-specific functions defined in each board's ddr.c */ 21 extern void fsl_ddr_board_options(memctl_options_t *popts, 22 dimm_params_t *pdimm, 23 unsigned int ctrl_num); 24 25 struct dynamic_odt { 26 unsigned int odt_rd_cfg; 27 unsigned int odt_wr_cfg; 28 unsigned int odt_rtt_norm; 29 unsigned int odt_rtt_wr; 30 }; 31 32 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 33 static const struct dynamic_odt single_Q[4] = { 34 { /* cs0 */ 35 FSL_DDR_ODT_NEVER, 36 FSL_DDR_ODT_CS_AND_OTHER_DIMM, 37 DDR3_RTT_20_OHM, 38 DDR3_RTT_120_OHM 39 }, 40 { /* cs1 */ 41 FSL_DDR_ODT_NEVER, 42 FSL_DDR_ODT_NEVER, /* tied high */ 43 DDR3_RTT_OFF, 44 DDR3_RTT_120_OHM 45 }, 46 { /* cs2 */ 47 FSL_DDR_ODT_NEVER, 48 FSL_DDR_ODT_CS_AND_OTHER_DIMM, 49 DDR3_RTT_20_OHM, 50 DDR3_RTT_120_OHM 51 }, 52 { /* cs3 */ 53 FSL_DDR_ODT_NEVER, 54 FSL_DDR_ODT_NEVER, /* tied high */ 55 DDR3_RTT_OFF, 56 DDR3_RTT_120_OHM 57 } 58 }; 59 60 static const struct dynamic_odt single_D[4] = { 61 { /* cs0 */ 62 FSL_DDR_ODT_NEVER, 63 FSL_DDR_ODT_ALL, 64 DDR3_RTT_40_OHM, 65 DDR3_RTT_OFF 66 }, 67 { /* cs1 */ 68 FSL_DDR_ODT_NEVER, 69 FSL_DDR_ODT_NEVER, 70 DDR3_RTT_OFF, 71 DDR3_RTT_OFF 72 }, 73 {0, 0, 0, 0}, 74 {0, 0, 0, 0} 75 }; 76 77 static const struct dynamic_odt single_S[4] = { 78 { /* cs0 */ 79 FSL_DDR_ODT_NEVER, 80 FSL_DDR_ODT_ALL, 81 DDR3_RTT_40_OHM, 82 DDR3_RTT_OFF 83 }, 84 {0, 0, 0, 0}, 85 {0, 0, 0, 0}, 86 {0, 0, 0, 0}, 87 }; 88 89 static const struct dynamic_odt dual_DD[4] = { 90 { /* cs0 */ 91 FSL_DDR_ODT_NEVER, 92 FSL_DDR_ODT_SAME_DIMM, 93 DDR3_RTT_120_OHM, 94 DDR3_RTT_OFF 95 }, 96 { /* cs1 */ 97 FSL_DDR_ODT_OTHER_DIMM, 98 FSL_DDR_ODT_OTHER_DIMM, 99 DDR3_RTT_30_OHM, 100 DDR3_RTT_OFF 101 }, 102 { /* cs2 */ 103 FSL_DDR_ODT_NEVER, 104 FSL_DDR_ODT_SAME_DIMM, 105 DDR3_RTT_120_OHM, 106 DDR3_RTT_OFF 107 }, 108 { /* cs3 */ 109 FSL_DDR_ODT_OTHER_DIMM, 110 FSL_DDR_ODT_OTHER_DIMM, 111 DDR3_RTT_30_OHM, 112 DDR3_RTT_OFF 113 } 114 }; 115 116 static const struct dynamic_odt dual_DS[4] = { 117 { /* cs0 */ 118 FSL_DDR_ODT_NEVER, 119 FSL_DDR_ODT_SAME_DIMM, 120 DDR3_RTT_120_OHM, 121 DDR3_RTT_OFF 122 }, 123 { /* cs1 */ 124 FSL_DDR_ODT_OTHER_DIMM, 125 FSL_DDR_ODT_OTHER_DIMM, 126 DDR3_RTT_30_OHM, 127 DDR3_RTT_OFF 128 }, 129 { /* cs2 */ 130 FSL_DDR_ODT_OTHER_DIMM, 131 FSL_DDR_ODT_ALL, 132 DDR3_RTT_20_OHM, 133 DDR3_RTT_120_OHM 134 }, 135 {0, 0, 0, 0} 136 }; 137 static const struct dynamic_odt dual_SD[4] = { 138 { /* cs0 */ 139 FSL_DDR_ODT_OTHER_DIMM, 140 FSL_DDR_ODT_ALL, 141 DDR3_RTT_20_OHM, 142 DDR3_RTT_120_OHM 143 }, 144 {0, 0, 0, 0}, 145 { /* cs2 */ 146 FSL_DDR_ODT_NEVER, 147 FSL_DDR_ODT_SAME_DIMM, 148 DDR3_RTT_120_OHM, 149 DDR3_RTT_OFF 150 }, 151 { /* cs3 */ 152 FSL_DDR_ODT_OTHER_DIMM, 153 FSL_DDR_ODT_OTHER_DIMM, 154 DDR3_RTT_20_OHM, 155 DDR3_RTT_OFF 156 } 157 }; 158 159 static const struct dynamic_odt dual_SS[4] = { 160 { /* cs0 */ 161 FSL_DDR_ODT_OTHER_DIMM, 162 FSL_DDR_ODT_ALL, 163 DDR3_RTT_30_OHM, 164 DDR3_RTT_120_OHM 165 }, 166 {0, 0, 0, 0}, 167 { /* cs2 */ 168 FSL_DDR_ODT_OTHER_DIMM, 169 FSL_DDR_ODT_ALL, 170 DDR3_RTT_30_OHM, 171 DDR3_RTT_120_OHM 172 }, 173 {0, 0, 0, 0} 174 }; 175 176 static const struct dynamic_odt dual_D0[4] = { 177 { /* cs0 */ 178 FSL_DDR_ODT_NEVER, 179 FSL_DDR_ODT_SAME_DIMM, 180 DDR3_RTT_40_OHM, 181 DDR3_RTT_OFF 182 }, 183 { /* cs1 */ 184 FSL_DDR_ODT_NEVER, 185 FSL_DDR_ODT_NEVER, 186 DDR3_RTT_OFF, 187 DDR3_RTT_OFF 188 }, 189 {0, 0, 0, 0}, 190 {0, 0, 0, 0} 191 }; 192 193 static const struct dynamic_odt dual_0D[4] = { 194 {0, 0, 0, 0}, 195 {0, 0, 0, 0}, 196 { /* cs2 */ 197 FSL_DDR_ODT_NEVER, 198 FSL_DDR_ODT_SAME_DIMM, 199 DDR3_RTT_40_OHM, 200 DDR3_RTT_OFF 201 }, 202 { /* cs3 */ 203 FSL_DDR_ODT_NEVER, 204 FSL_DDR_ODT_NEVER, 205 DDR3_RTT_OFF, 206 DDR3_RTT_OFF 207 } 208 }; 209 210 static const struct dynamic_odt dual_S0[4] = { 211 { /* cs0 */ 212 FSL_DDR_ODT_NEVER, 213 FSL_DDR_ODT_CS, 214 DDR3_RTT_40_OHM, 215 DDR3_RTT_OFF 216 }, 217 {0, 0, 0, 0}, 218 {0, 0, 0, 0}, 219 {0, 0, 0, 0} 220 221 }; 222 223 static const struct dynamic_odt dual_0S[4] = { 224 {0, 0, 0, 0}, 225 {0, 0, 0, 0}, 226 { /* cs2 */ 227 FSL_DDR_ODT_NEVER, 228 FSL_DDR_ODT_CS, 229 DDR3_RTT_40_OHM, 230 DDR3_RTT_OFF 231 }, 232 {0, 0, 0, 0} 233 234 }; 235 236 static const struct dynamic_odt odt_unknown[4] = { 237 { /* cs0 */ 238 FSL_DDR_ODT_NEVER, 239 FSL_DDR_ODT_CS, 240 DDR3_RTT_120_OHM, 241 DDR3_RTT_OFF 242 }, 243 { /* cs1 */ 244 FSL_DDR_ODT_NEVER, 245 FSL_DDR_ODT_CS, 246 DDR3_RTT_120_OHM, 247 DDR3_RTT_OFF 248 }, 249 { /* cs2 */ 250 FSL_DDR_ODT_NEVER, 251 FSL_DDR_ODT_CS, 252 DDR3_RTT_120_OHM, 253 DDR3_RTT_OFF 254 }, 255 { /* cs3 */ 256 FSL_DDR_ODT_NEVER, 257 FSL_DDR_ODT_CS, 258 DDR3_RTT_120_OHM, 259 DDR3_RTT_OFF 260 } 261 }; 262 #else /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */ 263 static const struct dynamic_odt single_Q[4] = { 264 {0, 0, 0, 0}, 265 {0, 0, 0, 0}, 266 {0, 0, 0, 0}, 267 {0, 0, 0, 0} 268 }; 269 270 static const struct dynamic_odt single_D[4] = { 271 { /* cs0 */ 272 FSL_DDR_ODT_NEVER, 273 FSL_DDR_ODT_ALL, 274 DDR2_RTT_150_OHM, 275 DDR2_RTT_OFF 276 }, 277 { /* cs1 */ 278 FSL_DDR_ODT_NEVER, 279 FSL_DDR_ODT_NEVER, 280 DDR2_RTT_OFF, 281 DDR2_RTT_OFF 282 }, 283 {0, 0, 0, 0}, 284 {0, 0, 0, 0} 285 }; 286 287 static const struct dynamic_odt single_S[4] = { 288 { /* cs0 */ 289 FSL_DDR_ODT_NEVER, 290 FSL_DDR_ODT_ALL, 291 DDR2_RTT_150_OHM, 292 DDR2_RTT_OFF 293 }, 294 {0, 0, 0, 0}, 295 {0, 0, 0, 0}, 296 {0, 0, 0, 0}, 297 }; 298 299 static const struct dynamic_odt dual_DD[4] = { 300 { /* cs0 */ 301 FSL_DDR_ODT_OTHER_DIMM, 302 FSL_DDR_ODT_OTHER_DIMM, 303 DDR2_RTT_75_OHM, 304 DDR2_RTT_OFF 305 }, 306 { /* cs1 */ 307 FSL_DDR_ODT_NEVER, 308 FSL_DDR_ODT_NEVER, 309 DDR2_RTT_OFF, 310 DDR2_RTT_OFF 311 }, 312 { /* cs2 */ 313 FSL_DDR_ODT_OTHER_DIMM, 314 FSL_DDR_ODT_OTHER_DIMM, 315 DDR2_RTT_75_OHM, 316 DDR2_RTT_OFF 317 }, 318 { /* cs3 */ 319 FSL_DDR_ODT_NEVER, 320 FSL_DDR_ODT_NEVER, 321 DDR2_RTT_OFF, 322 DDR2_RTT_OFF 323 } 324 }; 325 326 static const struct dynamic_odt dual_DS[4] = { 327 { /* cs0 */ 328 FSL_DDR_ODT_OTHER_DIMM, 329 FSL_DDR_ODT_OTHER_DIMM, 330 DDR2_RTT_75_OHM, 331 DDR2_RTT_OFF 332 }, 333 { /* cs1 */ 334 FSL_DDR_ODT_NEVER, 335 FSL_DDR_ODT_NEVER, 336 DDR2_RTT_OFF, 337 DDR2_RTT_OFF 338 }, 339 { /* cs2 */ 340 FSL_DDR_ODT_OTHER_DIMM, 341 FSL_DDR_ODT_OTHER_DIMM, 342 DDR2_RTT_75_OHM, 343 DDR2_RTT_OFF 344 }, 345 {0, 0, 0, 0} 346 }; 347 348 static const struct dynamic_odt dual_SD[4] = { 349 { /* cs0 */ 350 FSL_DDR_ODT_OTHER_DIMM, 351 FSL_DDR_ODT_OTHER_DIMM, 352 DDR2_RTT_75_OHM, 353 DDR2_RTT_OFF 354 }, 355 {0, 0, 0, 0}, 356 { /* cs2 */ 357 FSL_DDR_ODT_OTHER_DIMM, 358 FSL_DDR_ODT_OTHER_DIMM, 359 DDR2_RTT_75_OHM, 360 DDR2_RTT_OFF 361 }, 362 { /* cs3 */ 363 FSL_DDR_ODT_NEVER, 364 FSL_DDR_ODT_NEVER, 365 DDR2_RTT_OFF, 366 DDR2_RTT_OFF 367 } 368 }; 369 370 static const struct dynamic_odt dual_SS[4] = { 371 { /* cs0 */ 372 FSL_DDR_ODT_OTHER_DIMM, 373 FSL_DDR_ODT_OTHER_DIMM, 374 DDR2_RTT_75_OHM, 375 DDR2_RTT_OFF 376 }, 377 {0, 0, 0, 0}, 378 { /* cs2 */ 379 FSL_DDR_ODT_OTHER_DIMM, 380 FSL_DDR_ODT_OTHER_DIMM, 381 DDR2_RTT_75_OHM, 382 DDR2_RTT_OFF 383 }, 384 {0, 0, 0, 0} 385 }; 386 387 static const struct dynamic_odt dual_D0[4] = { 388 { /* cs0 */ 389 FSL_DDR_ODT_NEVER, 390 FSL_DDR_ODT_ALL, 391 DDR2_RTT_150_OHM, 392 DDR2_RTT_OFF 393 }, 394 { /* cs1 */ 395 FSL_DDR_ODT_NEVER, 396 FSL_DDR_ODT_NEVER, 397 DDR2_RTT_OFF, 398 DDR2_RTT_OFF 399 }, 400 {0, 0, 0, 0}, 401 {0, 0, 0, 0} 402 }; 403 404 static const struct dynamic_odt dual_0D[4] = { 405 {0, 0, 0, 0}, 406 {0, 0, 0, 0}, 407 { /* cs2 */ 408 FSL_DDR_ODT_NEVER, 409 FSL_DDR_ODT_ALL, 410 DDR2_RTT_150_OHM, 411 DDR2_RTT_OFF 412 }, 413 { /* cs3 */ 414 FSL_DDR_ODT_NEVER, 415 FSL_DDR_ODT_NEVER, 416 DDR2_RTT_OFF, 417 DDR2_RTT_OFF 418 } 419 }; 420 421 static const struct dynamic_odt dual_S0[4] = { 422 { /* cs0 */ 423 FSL_DDR_ODT_NEVER, 424 FSL_DDR_ODT_CS, 425 DDR2_RTT_150_OHM, 426 DDR2_RTT_OFF 427 }, 428 {0, 0, 0, 0}, 429 {0, 0, 0, 0}, 430 {0, 0, 0, 0} 431 432 }; 433 434 static const struct dynamic_odt dual_0S[4] = { 435 {0, 0, 0, 0}, 436 {0, 0, 0, 0}, 437 { /* cs2 */ 438 FSL_DDR_ODT_NEVER, 439 FSL_DDR_ODT_CS, 440 DDR2_RTT_150_OHM, 441 DDR2_RTT_OFF 442 }, 443 {0, 0, 0, 0} 444 445 }; 446 447 static const struct dynamic_odt odt_unknown[4] = { 448 { /* cs0 */ 449 FSL_DDR_ODT_NEVER, 450 FSL_DDR_ODT_CS, 451 DDR2_RTT_75_OHM, 452 DDR2_RTT_OFF 453 }, 454 { /* cs1 */ 455 FSL_DDR_ODT_NEVER, 456 FSL_DDR_ODT_NEVER, 457 DDR2_RTT_OFF, 458 DDR2_RTT_OFF 459 }, 460 { /* cs2 */ 461 FSL_DDR_ODT_NEVER, 462 FSL_DDR_ODT_CS, 463 DDR2_RTT_75_OHM, 464 DDR2_RTT_OFF 465 }, 466 { /* cs3 */ 467 FSL_DDR_ODT_NEVER, 468 FSL_DDR_ODT_NEVER, 469 DDR2_RTT_OFF, 470 DDR2_RTT_OFF 471 } 472 }; 473 #endif 474 475 /* 476 * Automatically seleect bank interleaving mode based on DIMMs 477 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null. 478 * This function only deal with one or two slots per controller. 479 */ 480 static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm) 481 { 482 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 483 if (pdimm[0].n_ranks == 4) 484 return FSL_DDR_CS0_CS1_CS2_CS3; 485 else if (pdimm[0].n_ranks == 2) 486 return FSL_DDR_CS0_CS1; 487 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 488 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 489 if (pdimm[0].n_ranks == 4) 490 return FSL_DDR_CS0_CS1_CS2_CS3; 491 #endif 492 if (pdimm[0].n_ranks == 2) { 493 if (pdimm[1].n_ranks == 2) 494 return FSL_DDR_CS0_CS1_CS2_CS3; 495 else 496 return FSL_DDR_CS0_CS1; 497 } 498 #endif 499 return 0; 500 } 501 502 unsigned int populate_memctl_options(int all_dimms_registered, 503 memctl_options_t *popts, 504 dimm_params_t *pdimm, 505 unsigned int ctrl_num) 506 { 507 unsigned int i; 508 char buffer[HWCONFIG_BUFFER_SIZE]; 509 char *buf = NULL; 510 #if defined(CONFIG_SYS_FSL_DDR3) || \ 511 defined(CONFIG_SYS_FSL_DDR2) || \ 512 defined(CONFIG_SYS_FSL_DDR4) 513 const struct dynamic_odt *pdodt = odt_unknown; 514 #endif 515 ulong ddr_freq; 516 517 /* 518 * Extract hwconfig from environment since we have not properly setup 519 * the environment but need it for ddr config params 520 */ 521 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) 522 buf = buffer; 523 524 #if defined(CONFIG_SYS_FSL_DDR3) || \ 525 defined(CONFIG_SYS_FSL_DDR2) || \ 526 defined(CONFIG_SYS_FSL_DDR4) 527 /* Chip select options. */ 528 if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) { 529 switch (pdimm[0].n_ranks) { 530 case 1: 531 pdodt = single_S; 532 break; 533 case 2: 534 pdodt = single_D; 535 break; 536 case 4: 537 pdodt = single_Q; 538 break; 539 } 540 } else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) { 541 switch (pdimm[0].n_ranks) { 542 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 543 case 4: 544 pdodt = single_Q; 545 if (pdimm[1].n_ranks) 546 printf("Error: Quad- and Dual-rank DIMMs " 547 "cannot be used together\n"); 548 break; 549 #endif 550 case 2: 551 switch (pdimm[1].n_ranks) { 552 case 2: 553 pdodt = dual_DD; 554 break; 555 case 1: 556 pdodt = dual_DS; 557 break; 558 case 0: 559 pdodt = dual_D0; 560 break; 561 } 562 break; 563 case 1: 564 switch (pdimm[1].n_ranks) { 565 case 2: 566 pdodt = dual_SD; 567 break; 568 case 1: 569 pdodt = dual_SS; 570 break; 571 case 0: 572 pdodt = dual_S0; 573 break; 574 } 575 break; 576 case 0: 577 switch (pdimm[1].n_ranks) { 578 case 2: 579 pdodt = dual_0D; 580 break; 581 case 1: 582 pdodt = dual_0S; 583 break; 584 } 585 break; 586 } 587 } 588 #endif 589 590 /* Pick chip-select local options. */ 591 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 592 #if defined(CONFIG_SYS_FSL_DDR3) || \ 593 defined(CONFIG_SYS_FSL_DDR2) || \ 594 defined(CONFIG_SYS_FSL_DDR4) 595 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg; 596 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg; 597 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm; 598 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr; 599 #else 600 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; 601 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; 602 #endif 603 popts->cs_local_opts[i].auto_precharge = 0; 604 } 605 606 /* Pick interleaving mode. */ 607 608 /* 609 * 0 = no interleaving 610 * 1 = interleaving between 2 controllers 611 */ 612 popts->memctl_interleaving = 0; 613 614 /* 615 * 0 = cacheline 616 * 1 = page 617 * 2 = (logical) bank 618 * 3 = superbank (only if CS interleaving is enabled) 619 */ 620 popts->memctl_interleaving_mode = 0; 621 622 /* 623 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl 624 * 1: page: bit to the left of the column bits selects the memctl 625 * 2: bank: bit to the left of the bank bits selects the memctl 626 * 3: superbank: bit to the left of the chip select selects the memctl 627 * 628 * NOTE: ba_intlv (rank interleaving) is independent of memory 629 * controller interleaving; it is only within a memory controller. 630 * Must use superbank interleaving if rank interleaving is used and 631 * memory controller interleaving is enabled. 632 */ 633 634 /* 635 * 0 = no 636 * 0x40 = CS0,CS1 637 * 0x20 = CS2,CS3 638 * 0x60 = CS0,CS1 + CS2,CS3 639 * 0x04 = CS0,CS1,CS2,CS3 640 */ 641 popts->ba_intlv_ctl = 0; 642 643 /* Memory Organization Parameters */ 644 popts->registered_dimm_en = all_dimms_registered; 645 646 /* Operational Mode Paramters */ 647 648 /* Pick ECC modes */ 649 popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */ 650 #ifdef CONFIG_DDR_ECC 651 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) { 652 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf)) 653 popts->ecc_mode = 1; 654 } else 655 popts->ecc_mode = 1; 656 #endif 657 popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ 658 659 /* 660 * Choose DQS config 661 * 0 for DDR1 662 * 1 for DDR2 663 */ 664 #if defined(CONFIG_SYS_FSL_DDR1) 665 popts->dqs_config = 0; 666 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3) 667 popts->dqs_config = 1; 668 #endif 669 670 /* Choose self-refresh during sleep. */ 671 popts->self_refresh_in_sleep = 1; 672 673 /* Choose dynamic power management mode. */ 674 popts->dynamic_power = 0; 675 676 /* 677 * check first dimm for primary sdram width 678 * presuming all dimms are similar 679 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit 680 */ 681 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2) 682 if (pdimm[0].n_ranks != 0) { 683 if ((pdimm[0].data_width >= 64) && \ 684 (pdimm[0].data_width <= 72)) 685 popts->data_bus_width = 0; 686 else if ((pdimm[0].data_width >= 32) || \ 687 (pdimm[0].data_width <= 40)) 688 popts->data_bus_width = 1; 689 else { 690 panic("Error: data width %u is invalid!\n", 691 pdimm[0].data_width); 692 } 693 } 694 #else 695 if (pdimm[0].n_ranks != 0) { 696 if (pdimm[0].primary_sdram_width == 64) 697 popts->data_bus_width = 0; 698 else if (pdimm[0].primary_sdram_width == 32) 699 popts->data_bus_width = 1; 700 else if (pdimm[0].primary_sdram_width == 16) 701 popts->data_bus_width = 2; 702 else { 703 panic("Error: primary sdram width %u is invalid!\n", 704 pdimm[0].primary_sdram_width); 705 } 706 } 707 #endif 708 709 popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0; 710 711 /* Choose burst length. */ 712 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 713 #if defined(CONFIG_E500MC) 714 popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */ 715 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ 716 #else 717 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) { 718 /* 32-bit or 16-bit bus */ 719 popts->otf_burst_chop_en = 0; 720 popts->burst_length = DDR_BL8; 721 } else { 722 popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */ 723 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */ 724 } 725 #endif 726 #else 727 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */ 728 #endif 729 730 /* Choose ddr controller address mirror mode */ 731 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 732 popts->mirrored_dimm = pdimm[0].mirrored_dimm; 733 #endif 734 735 /* Global Timing Parameters. */ 736 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps()); 737 738 /* Pick a caslat override. */ 739 popts->cas_latency_override = 0; 740 popts->cas_latency_override_value = 3; 741 if (popts->cas_latency_override) { 742 debug("using caslat override value = %u\n", 743 popts->cas_latency_override_value); 744 } 745 746 /* Decide whether to use the computed derated latency */ 747 popts->use_derated_caslat = 0; 748 749 /* Choose an additive latency. */ 750 popts->additive_latency_override = 0; 751 popts->additive_latency_override_value = 3; 752 if (popts->additive_latency_override) { 753 debug("using additive latency override value = %u\n", 754 popts->additive_latency_override_value); 755 } 756 757 /* 758 * 2T_EN setting 759 * 760 * Factors to consider for 2T_EN: 761 * - number of DIMMs installed 762 * - number of components, number of active ranks 763 * - how much time you want to spend playing around 764 */ 765 popts->twot_en = 0; 766 popts->threet_en = 0; 767 768 /* for RDIMM, address parity enable */ 769 popts->ap_en = 1; 770 771 /* 772 * BSTTOPRE precharge interval 773 * 774 * Set this to 0 for global auto precharge 775 * The value of 0x100 has been used for DDR1, DDR2, DDR3. 776 * It is not wrong. Any value should be OK. The performance depends on 777 * applications. There is no one good value for all. 778 */ 779 popts->bstopre = 0x100; 780 781 /* Minimum CKE pulse width -- tCKE(MIN) */ 782 popts->tcke_clock_pulse_width_ps 783 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR); 784 785 /* 786 * Window for four activates -- tFAW 787 * 788 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only 789 * FIXME: varies depending upon number of column addresses or data 790 * FIXME: width, was considering looking at pdimm->primary_sdram_width 791 */ 792 #if defined(CONFIG_SYS_FSL_DDR1) 793 popts->tfaw_window_four_activates_ps = mclk_to_picos(1); 794 795 #elif defined(CONFIG_SYS_FSL_DDR2) 796 /* 797 * x4/x8; some datasheets have 35000 798 * x16 wide columns only? Use 50000? 799 */ 800 popts->tfaw_window_four_activates_ps = 37500; 801 802 #else 803 popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps; 804 #endif 805 popts->zq_en = 0; 806 popts->wrlvl_en = 0; 807 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 808 /* 809 * due to ddr3 dimm is fly-by topology 810 * we suggest to enable write leveling to 811 * meet the tQDSS under different loading. 812 */ 813 popts->wrlvl_en = 1; 814 popts->zq_en = 1; 815 popts->wrlvl_override = 0; 816 #endif 817 818 /* 819 * Check interleaving configuration from environment. 820 * Please refer to doc/README.fsl-ddr for the detail. 821 * 822 * If memory controller interleaving is enabled, then the data 823 * bus widths must be programmed identically for all memory controllers. 824 * 825 * Attempt to set all controllers to the same chip select 826 * interleaving mode. It will do a best effort to get the 827 * requested ranks interleaved together such that the result 828 * should be a subset of the requested configuration. 829 * 830 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving 831 * with 256 Byte is enabled. 832 */ 833 #if (CONFIG_NUM_DDR_CONTROLLERS > 1) 834 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) 835 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B 836 ; 837 #else 838 goto done; 839 #endif 840 if (pdimm[0].n_ranks == 0) { 841 printf("There is no rank on CS0 for controller %d.\n", ctrl_num); 842 popts->memctl_interleaving = 0; 843 goto done; 844 } 845 popts->memctl_interleaving = 1; 846 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B 847 popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING; 848 popts->memctl_interleaving = 1; 849 debug("256 Byte interleaving\n"); 850 goto done; 851 #endif 852 /* 853 * test null first. if CONFIG_HWCONFIG is not defined 854 * hwconfig_arg_cmp returns non-zero 855 */ 856 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv", 857 "null", buf)) { 858 popts->memctl_interleaving = 0; 859 debug("memory controller interleaving disabled.\n"); 860 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 861 "ctlr_intlv", 862 "cacheline", buf)) { 863 popts->memctl_interleaving_mode = 864 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 865 0 : FSL_DDR_CACHE_LINE_INTERLEAVING; 866 popts->memctl_interleaving = 867 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 868 0 : 1; 869 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 870 "ctlr_intlv", 871 "page", buf)) { 872 popts->memctl_interleaving_mode = 873 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 874 0 : FSL_DDR_PAGE_INTERLEAVING; 875 popts->memctl_interleaving = 876 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 877 0 : 1; 878 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 879 "ctlr_intlv", 880 "bank", buf)) { 881 popts->memctl_interleaving_mode = 882 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 883 0 : FSL_DDR_BANK_INTERLEAVING; 884 popts->memctl_interleaving = 885 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 886 0 : 1; 887 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 888 "ctlr_intlv", 889 "superbank", buf)) { 890 popts->memctl_interleaving_mode = 891 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 892 0 : FSL_DDR_SUPERBANK_INTERLEAVING; 893 popts->memctl_interleaving = 894 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ? 895 0 : 1; 896 #if (CONFIG_NUM_DDR_CONTROLLERS == 3) 897 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 898 "ctlr_intlv", 899 "3way_1KB", buf)) { 900 popts->memctl_interleaving_mode = 901 FSL_DDR_3WAY_1KB_INTERLEAVING; 902 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 903 "ctlr_intlv", 904 "3way_4KB", buf)) { 905 popts->memctl_interleaving_mode = 906 FSL_DDR_3WAY_4KB_INTERLEAVING; 907 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 908 "ctlr_intlv", 909 "3way_8KB", buf)) { 910 popts->memctl_interleaving_mode = 911 FSL_DDR_3WAY_8KB_INTERLEAVING; 912 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4) 913 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 914 "ctlr_intlv", 915 "4way_1KB", buf)) { 916 popts->memctl_interleaving_mode = 917 FSL_DDR_4WAY_1KB_INTERLEAVING; 918 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 919 "ctlr_intlv", 920 "4way_4KB", buf)) { 921 popts->memctl_interleaving_mode = 922 FSL_DDR_4WAY_4KB_INTERLEAVING; 923 } else if (hwconfig_subarg_cmp_f("fsl_ddr", 924 "ctlr_intlv", 925 "4way_8KB", buf)) { 926 popts->memctl_interleaving_mode = 927 FSL_DDR_4WAY_8KB_INTERLEAVING; 928 #endif 929 } else { 930 popts->memctl_interleaving = 0; 931 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n"); 932 } 933 done: 934 #endif 935 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) && 936 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) { 937 /* test null first. if CONFIG_HWCONFIG is not defined, 938 * hwconfig_subarg_cmp_f returns non-zero */ 939 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 940 "null", buf)) 941 debug("bank interleaving disabled.\n"); 942 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 943 "cs0_cs1", buf)) 944 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1; 945 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 946 "cs2_cs3", buf)) 947 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3; 948 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 949 "cs0_cs1_and_cs2_cs3", buf)) 950 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3; 951 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 952 "cs0_cs1_cs2_cs3", buf)) 953 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3; 954 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv", 955 "auto", buf)) 956 popts->ba_intlv_ctl = auto_bank_intlv(pdimm); 957 else 958 printf("hwconfig has unrecognized parameter for bank_intlv.\n"); 959 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { 960 case FSL_DDR_CS0_CS1_CS2_CS3: 961 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 962 if (pdimm[0].n_ranks < 4) { 963 popts->ba_intlv_ctl = 0; 964 printf("Not enough bank(chip-select) for " 965 "CS0+CS1+CS2+CS3 on controller %d, " 966 "interleaving disabled!\n", ctrl_num); 967 } 968 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 969 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 970 if (pdimm[0].n_ranks == 4) 971 break; 972 #endif 973 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) { 974 popts->ba_intlv_ctl = 0; 975 printf("Not enough bank(chip-select) for " 976 "CS0+CS1+CS2+CS3 on controller %d, " 977 "interleaving disabled!\n", ctrl_num); 978 } 979 if (pdimm[0].capacity != pdimm[1].capacity) { 980 popts->ba_intlv_ctl = 0; 981 printf("Not identical DIMM size for " 982 "CS0+CS1+CS2+CS3 on controller %d, " 983 "interleaving disabled!\n", ctrl_num); 984 } 985 #endif 986 break; 987 case FSL_DDR_CS0_CS1: 988 if (pdimm[0].n_ranks < 2) { 989 popts->ba_intlv_ctl = 0; 990 printf("Not enough bank(chip-select) for " 991 "CS0+CS1 on controller %d, " 992 "interleaving disabled!\n", ctrl_num); 993 } 994 break; 995 case FSL_DDR_CS2_CS3: 996 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 997 if (pdimm[0].n_ranks < 4) { 998 popts->ba_intlv_ctl = 0; 999 printf("Not enough bank(chip-select) for CS2+CS3 " 1000 "on controller %d, interleaving disabled!\n", ctrl_num); 1001 } 1002 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 1003 if (pdimm[1].n_ranks < 2) { 1004 popts->ba_intlv_ctl = 0; 1005 printf("Not enough bank(chip-select) for CS2+CS3 " 1006 "on controller %d, interleaving disabled!\n", ctrl_num); 1007 } 1008 #endif 1009 break; 1010 case FSL_DDR_CS0_CS1_AND_CS2_CS3: 1011 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) 1012 if (pdimm[0].n_ranks < 4) { 1013 popts->ba_intlv_ctl = 0; 1014 printf("Not enough bank(CS) for CS0+CS1 and " 1015 "CS2+CS3 on controller %d, " 1016 "interleaving disabled!\n", ctrl_num); 1017 } 1018 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2) 1019 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) { 1020 popts->ba_intlv_ctl = 0; 1021 printf("Not enough bank(CS) for CS0+CS1 and " 1022 "CS2+CS3 on controller %d, " 1023 "interleaving disabled!\n", ctrl_num); 1024 } 1025 #endif 1026 break; 1027 default: 1028 popts->ba_intlv_ctl = 0; 1029 break; 1030 } 1031 } 1032 1033 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) { 1034 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf)) 1035 popts->addr_hash = 0; 1036 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", 1037 "true", buf)) 1038 popts->addr_hash = 1; 1039 } 1040 1041 if (pdimm[0].n_ranks == 4) 1042 popts->quad_rank_present = 1; 1043 1044 ddr_freq = get_ddr_freq(0) / 1000000; 1045 if (popts->registered_dimm_en) { 1046 popts->rcw_override = 1; 1047 popts->rcw_1 = 0x000a5a00; 1048 if (ddr_freq <= 800) 1049 popts->rcw_2 = 0x00000000; 1050 else if (ddr_freq <= 1066) 1051 popts->rcw_2 = 0x00100000; 1052 else if (ddr_freq <= 1333) 1053 popts->rcw_2 = 0x00200000; 1054 else 1055 popts->rcw_2 = 0x00300000; 1056 } 1057 1058 fsl_ddr_board_options(popts, pdimm, ctrl_num); 1059 1060 return 0; 1061 } 1062 1063 void check_interleaving_options(fsl_ddr_info_t *pinfo) 1064 { 1065 int i, j, k, check_n_ranks, intlv_invalid = 0; 1066 unsigned int check_intlv, check_n_row_addr, check_n_col_addr; 1067 unsigned long long check_rank_density; 1068 struct dimm_params_s *dimm; 1069 /* 1070 * Check if all controllers are configured for memory 1071 * controller interleaving. Identical dimms are recommended. At least 1072 * the size, row and col address should be checked. 1073 */ 1074 j = 0; 1075 check_n_ranks = pinfo->dimm_params[0][0].n_ranks; 1076 check_rank_density = pinfo->dimm_params[0][0].rank_density; 1077 check_n_row_addr = pinfo->dimm_params[0][0].n_row_addr; 1078 check_n_col_addr = pinfo->dimm_params[0][0].n_col_addr; 1079 check_intlv = pinfo->memctl_opts[0].memctl_interleaving_mode; 1080 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { 1081 dimm = &pinfo->dimm_params[i][0]; 1082 if (!pinfo->memctl_opts[i].memctl_interleaving) { 1083 continue; 1084 } else if (((check_rank_density != dimm->rank_density) || 1085 (check_n_ranks != dimm->n_ranks) || 1086 (check_n_row_addr != dimm->n_row_addr) || 1087 (check_n_col_addr != dimm->n_col_addr) || 1088 (check_intlv != 1089 pinfo->memctl_opts[i].memctl_interleaving_mode))){ 1090 intlv_invalid = 1; 1091 break; 1092 } else { 1093 j++; 1094 } 1095 1096 } 1097 if (intlv_invalid) { 1098 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 1099 pinfo->memctl_opts[i].memctl_interleaving = 0; 1100 printf("Not all DIMMs are identical. " 1101 "Memory controller interleaving disabled.\n"); 1102 } else { 1103 switch (check_intlv) { 1104 case FSL_DDR_256B_INTERLEAVING: 1105 case FSL_DDR_CACHE_LINE_INTERLEAVING: 1106 case FSL_DDR_PAGE_INTERLEAVING: 1107 case FSL_DDR_BANK_INTERLEAVING: 1108 case FSL_DDR_SUPERBANK_INTERLEAVING: 1109 if (3 == CONFIG_NUM_DDR_CONTROLLERS) 1110 k = 2; 1111 else 1112 k = CONFIG_NUM_DDR_CONTROLLERS; 1113 break; 1114 case FSL_DDR_3WAY_1KB_INTERLEAVING: 1115 case FSL_DDR_3WAY_4KB_INTERLEAVING: 1116 case FSL_DDR_3WAY_8KB_INTERLEAVING: 1117 case FSL_DDR_4WAY_1KB_INTERLEAVING: 1118 case FSL_DDR_4WAY_4KB_INTERLEAVING: 1119 case FSL_DDR_4WAY_8KB_INTERLEAVING: 1120 default: 1121 k = CONFIG_NUM_DDR_CONTROLLERS; 1122 break; 1123 } 1124 debug("%d of %d controllers are interleaving.\n", j, k); 1125 if (j && (j != k)) { 1126 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) 1127 pinfo->memctl_opts[i].memctl_interleaving = 0; 1128 printf("Not all controllers have compatible " 1129 "interleaving mode. All disabled.\n"); 1130 } 1131 } 1132 debug("Checking interleaving options completed\n"); 1133 } 1134 1135 int fsl_use_spd(void) 1136 { 1137 int use_spd = 0; 1138 1139 #ifdef CONFIG_DDR_SPD 1140 char buffer[HWCONFIG_BUFFER_SIZE]; 1141 char *buf = NULL; 1142 1143 /* 1144 * Extract hwconfig from environment since we have not properly setup 1145 * the environment but need it for ddr config params 1146 */ 1147 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) 1148 buf = buffer; 1149 1150 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ 1151 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) { 1152 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf)) 1153 use_spd = 1; 1154 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", 1155 "fixed", buf)) 1156 use_spd = 0; 1157 else 1158 use_spd = 1; 1159 } else 1160 use_spd = 1; 1161 #endif 1162 1163 return use_spd; 1164 } 1165