zynqmp.c (cb7ea82059069c6509c26b1f705982c6a919a3fe) zynqmp.c (6fe6f1350990c28d3675392cc273cb3df8c31389)
1/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <netdev.h>
1/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <netdev.h>
10#include <ahci.h>
11#include <scsi.h>
10#include <asm/arch/hardware.h>
11#include <asm/arch/sys_proto.h>
12#include <asm/io.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
16int board_init(void)
17{

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46{
47 return 0;
48}
49
50void reset_cpu(ulong addr)
51{
52}
53
12#include <asm/arch/hardware.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/io.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18int board_init(void)
19{

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48{
49 return 0;
50}
51
52void reset_cpu(ulong addr)
53{
54}
55
56#ifdef CONFIG_SCSI_AHCI_PLAT
57void scsi_init(void)
58{
59 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
60 scsi_scan(1);
61}
62#endif
63
54int board_eth_init(bd_t *bis)
55{
56 u32 ret = 0;
57
58#if defined(CONFIG_ZYNQ_GEM)
59# if defined(CONFIG_ZYNQ_GEM0)
60 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
61 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);

--- 59 unchanged lines hidden --- 		64int board_eth_init(bd_t *bis)
65{
66 u32 ret = 0;
67
68#if defined(CONFIG_ZYNQ_GEM)
69# if defined(CONFIG_ZYNQ_GEM0)
70 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
71 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);

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