1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <netdev.h> 10 #include <ahci.h> 11 #include <scsi.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/io.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 int board_init(void) 19 { 20 return 0; 21 } 22 23 int board_early_init_r(void) 24 { 25 u32 val; 26 27 val = readl(&crlapb_base->timestamp_ref_ctrl); 28 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; 29 writel(val, &crlapb_base->timestamp_ref_ctrl); 30 31 /* Program freq register in System counter and enable system counter */ 32 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); 33 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | 34 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, 35 &iou_scntr->counter_control_register); 36 37 return 0; 38 } 39 40 int dram_init(void) 41 { 42 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 43 44 return 0; 45 } 46 47 int timer_init(void) 48 { 49 return 0; 50 } 51 52 void reset_cpu(ulong addr) 53 { 54 } 55 56 #ifdef CONFIG_SCSI_AHCI_PLAT 57 void scsi_init(void) 58 { 59 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR); 60 scsi_scan(1); 61 } 62 #endif 63 64 int board_eth_init(bd_t *bis) 65 { 66 u32 ret = 0; 67 68 #if defined(CONFIG_ZYNQ_GEM) 69 # if defined(CONFIG_ZYNQ_GEM0) 70 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, 71 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); 72 # endif 73 # if defined(CONFIG_ZYNQ_GEM1) 74 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, 75 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); 76 # endif 77 # if defined(CONFIG_ZYNQ_GEM2) 78 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2, 79 CONFIG_ZYNQ_GEM_PHY_ADDR2, 0); 80 # endif 81 # if defined(CONFIG_ZYNQ_GEM3) 82 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3, 83 CONFIG_ZYNQ_GEM_PHY_ADDR3, 0); 84 # endif 85 #endif 86 return ret; 87 } 88 89 #ifdef CONFIG_CMD_MMC 90 int board_mmc_init(bd_t *bd) 91 { 92 int ret = 0; 93 94 u32 ver = zynqmp_get_silicon_version(); 95 96 if (ver != ZYNQMP_CSU_VERSION_VELOCE) { 97 #if defined(CONFIG_ZYNQ_SDHCI) 98 # if defined(CONFIG_ZYNQ_SDHCI0) 99 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); 100 # endif 101 # if defined(CONFIG_ZYNQ_SDHCI1) 102 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); 103 # endif 104 #endif 105 } 106 107 return ret; 108 } 109 #endif 110 111 int board_late_init(void) 112 { 113 u32 reg = 0; 114 u8 bootmode; 115 116 reg = readl(&crlapb_base->boot_mode); 117 bootmode = reg & BOOT_MODES_MASK; 118 119 switch (bootmode) { 120 case SD_MODE: 121 case EMMC_MODE: 122 setenv("modeboot", "sdboot"); 123 break; 124 default: 125 printf("Invalid Boot Mode:0x%x\n", bootmode); 126 break; 127 } 128 129 return 0; 130 } 131