zynqmp.c (6889ca7198f68691ddd7923268040eb7f4e6d3ff) zynqmp.c (d9ae52c8f081e30cfceafc0ddb7f29d4ecd36d00)
1/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>

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60#ifdef CONFIG_SCSI_AHCI_PLAT
61void scsi_init(void)
62{
63 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
64 scsi_scan(1);
65}
66#endif
67
1/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>

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60#ifdef CONFIG_SCSI_AHCI_PLAT
61void scsi_init(void)
62{
63 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
64 scsi_scan(1);
65}
66#endif
67
68#ifdef CONFIG_CMD_MMC
69int board_mmc_init(bd_t *bd)
70{
71 int ret = 0;
72
73 u32 ver = zynqmp_get_silicon_version();
74
75 if (ver != ZYNQMP_CSU_VERSION_VELOCE) {
76#if defined(CONFIG_ZYNQ_SDHCI)
77# if defined(CONFIG_ZYNQ_SDHCI0)
78 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
79# endif
80# if defined(CONFIG_ZYNQ_SDHCI1)
81 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
82# endif
83#endif
84 }
85
86 return ret;
87}
88#endif
89
90int board_late_init(void)
91{
92 u32 reg = 0;
93 u8 bootmode;
94
95 reg = readl(&crlapb_base->boot_mode);
96 bootmode = reg & BOOT_MODES_MASK;
97

--- 44 unchanged lines hidden --- 		68int board_late_init(void)
69{
70 u32 reg = 0;
71 u8 bootmode;
72
73 reg = readl(&crlapb_base->boot_mode);
74 bootmode = reg & BOOT_MODES_MASK;
75

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