| Kconfig (5f88ed5cde04612e5b4520327b82d81a3f5493a0) | Kconfig (2d934e5703b712686c3ec67f6d5eeb137c68805d) |
|---|---|
| 1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7config USE_PRIVATE_LIBGCC 8 default y --- 342 unchanged lines hidden (view full) --- 351source "arch/x86/cpu/queensbay/Kconfig" 352 353source "board/coreboot/coreboot/Kconfig" 354 355source "board/google/chromebook_link/Kconfig" 356 357source "board/intel/crownbay/Kconfig" 358 | 1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7config USE_PRIVATE_LIBGCC 8 default y --- 342 unchanged lines hidden (view full) --- 351source "arch/x86/cpu/queensbay/Kconfig" 352 353source "board/coreboot/coreboot/Kconfig" 354 355source "board/google/chromebook_link/Kconfig" 356 357source "board/intel/crownbay/Kconfig" 358 |
| 359config PCIE_ECAM_BASE 360 hex 361 default 0xe0000000 362 help 363 This is the memory-mapped address of PCI configuration space, which 364 is only available through the Enhanced Configuration Access 365 Mechanism (ECAM) with PCI Express. It can be set up almost 366 anywhere. Before it is set up, it is possible to access PCI 367 configuration space through I/O access, but memory access is more 368 convenient. Using this, PCI can be scanned and configured. This 369 should be set to a region that does not conflict with memory 370 assigned to PCI devices - i.e. the memory and prefetch regions, as 371 passed to pci_set_region(). 372 |
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| 359endmenu | 373endmenu |