cpu.h (d1e8e8ecc3d2a1a72504912d671f1cbbac1b06e5) cpu.h (1f5c00cfdb8114c1e3a13426588ceb64f82c9ddb)
1#ifndef SPARC_CPU_H
2#define SPARC_CPU_H
3
4#include "qemu-common.h"
5#include "qemu/bswap.h"
6#include "cpu-qom.h"
7
8#define ALIGNED_ONLY

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414 uint32_t pil_in; /* incoming interrupt level bitmap */
415#if !defined(TARGET_SPARC64)
416 int psref; /* enable fpu */
417#endif
418 int interrupt_index;
419 /* NOTE: we allow 8 more registers to handle wrapping */
420 target_ulong regbase[MAX_NWINDOWS * 16 + 8];
421
1#ifndef SPARC_CPU_H
2#define SPARC_CPU_H
3
4#include "qemu-common.h"
5#include "qemu/bswap.h"
6#include "cpu-qom.h"
7
8#define ALIGNED_ONLY

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414 uint32_t pil_in; /* incoming interrupt level bitmap */
415#if !defined(TARGET_SPARC64)
416 int psref; /* enable fpu */
417#endif
418 int interrupt_index;
419 /* NOTE: we allow 8 more registers to handle wrapping */
420 target_ulong regbase[MAX_NWINDOWS * 16 + 8];
421
422 /* Fields up to this point are cleared by a CPU reset */
423 struct {} end_reset_fields;
424
422 CPU_COMMON
423
424 /* Fields from here on are preserved across CPU reset. */
425 target_ulong version;
426 uint32_t nwindows;
427
428 /* MMU regs */
429#if defined(TARGET_SPARC64)

--- 350 unchanged lines hidden --- 		425 CPU_COMMON
426
427 /* Fields from here on are preserved across CPU reset. */
428 target_ulong version;
429 uint32_t nwindows;
430
431 /* MMU regs */
432#if defined(TARGET_SPARC64)

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