1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu-common.h" 5 #include "qemu/bswap.h" 6 #include "cpu-qom.h" 7 8 #define ALIGNED_ONLY 9 10 #if !defined(TARGET_SPARC64) 11 #define TARGET_LONG_BITS 32 12 #define TARGET_DPREGS 16 13 #define TARGET_PAGE_BITS 12 /* 4k */ 14 #define TARGET_PHYS_ADDR_SPACE_BITS 36 15 #define TARGET_VIRT_ADDR_SPACE_BITS 32 16 #else 17 #define TARGET_LONG_BITS 64 18 #define TARGET_DPREGS 32 19 #define TARGET_PAGE_BITS 13 /* 8k */ 20 #define TARGET_PHYS_ADDR_SPACE_BITS 41 21 # ifdef TARGET_ABI32 22 # define TARGET_VIRT_ADDR_SPACE_BITS 32 23 # else 24 # define TARGET_VIRT_ADDR_SPACE_BITS 44 25 # endif 26 #endif 27 28 #define CPUArchState struct CPUSPARCState 29 30 #include "exec/cpu-defs.h" 31 32 #include "fpu/softfloat.h" 33 34 /*#define EXCP_INTERRUPT 0x100*/ 35 36 /* trap definitions */ 37 #ifndef TARGET_SPARC64 38 #define TT_TFAULT 0x01 39 #define TT_ILL_INSN 0x02 40 #define TT_PRIV_INSN 0x03 41 #define TT_NFPU_INSN 0x04 42 #define TT_WIN_OVF 0x05 43 #define TT_WIN_UNF 0x06 44 #define TT_UNALIGNED 0x07 45 #define TT_FP_EXCP 0x08 46 #define TT_DFAULT 0x09 47 #define TT_TOVF 0x0a 48 #define TT_EXTINT 0x10 49 #define TT_CODE_ACCESS 0x21 50 #define TT_UNIMP_FLUSH 0x25 51 #define TT_DATA_ACCESS 0x29 52 #define TT_DIV_ZERO 0x2a 53 #define TT_NCP_INSN 0x24 54 #define TT_TRAP 0x80 55 #else 56 #define TT_POWER_ON_RESET 0x01 57 #define TT_TFAULT 0x08 58 #define TT_CODE_ACCESS 0x0a 59 #define TT_ILL_INSN 0x10 60 #define TT_UNIMP_FLUSH TT_ILL_INSN 61 #define TT_PRIV_INSN 0x11 62 #define TT_NFPU_INSN 0x20 63 #define TT_FP_EXCP 0x21 64 #define TT_TOVF 0x23 65 #define TT_CLRWIN 0x24 66 #define TT_DIV_ZERO 0x28 67 #define TT_DFAULT 0x30 68 #define TT_DATA_ACCESS 0x32 69 #define TT_UNALIGNED 0x34 70 #define TT_PRIV_ACT 0x37 71 #define TT_EXTINT 0x40 72 #define TT_IVEC 0x60 73 #define TT_TMISS 0x64 74 #define TT_DMISS 0x68 75 #define TT_DPROT 0x6c 76 #define TT_SPILL 0x80 77 #define TT_FILL 0xc0 78 #define TT_WOTHER (1 << 5) 79 #define TT_TRAP 0x100 80 #endif 81 82 #define PSR_NEG_SHIFT 23 83 #define PSR_NEG (1 << PSR_NEG_SHIFT) 84 #define PSR_ZERO_SHIFT 22 85 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 86 #define PSR_OVF_SHIFT 21 87 #define PSR_OVF (1 << PSR_OVF_SHIFT) 88 #define PSR_CARRY_SHIFT 20 89 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 90 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 91 #if !defined(TARGET_SPARC64) 92 #define PSR_EF (1<<12) 93 #define PSR_PIL 0xf00 94 #define PSR_S (1<<7) 95 #define PSR_PS (1<<6) 96 #define PSR_ET (1<<5) 97 #define PSR_CWP 0x1f 98 #endif 99 100 #define CC_SRC (env->cc_src) 101 #define CC_SRC2 (env->cc_src2) 102 #define CC_DST (env->cc_dst) 103 #define CC_OP (env->cc_op) 104 105 /* Even though lazy evaluation of CPU condition codes tends to be less 106 * important on RISC systems where condition codes are only updated 107 * when explicitly requested, SPARC uses it to update 32-bit and 64-bit 108 * condition codes. 109 */ 110 enum { 111 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 112 CC_OP_FLAGS, /* all cc are back in status register */ 113 CC_OP_DIV, /* modify N, Z and V, C = 0*/ 114 CC_OP_ADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 115 CC_OP_ADDX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 116 CC_OP_TADD, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 117 CC_OP_TADDTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ 118 CC_OP_SUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 119 CC_OP_SUBX, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 120 CC_OP_TSUB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ 121 CC_OP_TSUBTV, /* modify all flags except V, CC_DST = res, CC_SRC = src1 */ 122 CC_OP_LOGIC, /* modify N and Z, C = V = 0, CC_DST = res */ 123 CC_OP_NB, 124 }; 125 126 /* Trap base register */ 127 #define TBR_BASE_MASK 0xfffff000 128 129 #if defined(TARGET_SPARC64) 130 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 131 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 132 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 133 #define PS_CLE (1<<9) /* UA2007 */ 134 #define PS_TLE (1<<8) /* UA2007 */ 135 #define PS_RMO (1<<7) 136 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 137 #define PS_PEF (1<<4) /* enable fpu */ 138 #define PS_AM (1<<3) /* address mask */ 139 #define PS_PRIV (1<<2) 140 #define PS_IE (1<<1) 141 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 142 143 #define FPRS_FEF (1<<2) 144 145 #define HS_PRIV (1<<2) 146 #endif 147 148 /* Fcc */ 149 #define FSR_RD1 (1ULL << 31) 150 #define FSR_RD0 (1ULL << 30) 151 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 152 #define FSR_RD_NEAREST 0 153 #define FSR_RD_ZERO FSR_RD0 154 #define FSR_RD_POS FSR_RD1 155 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 156 157 #define FSR_NVM (1ULL << 27) 158 #define FSR_OFM (1ULL << 26) 159 #define FSR_UFM (1ULL << 25) 160 #define FSR_DZM (1ULL << 24) 161 #define FSR_NXM (1ULL << 23) 162 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 163 164 #define FSR_NVA (1ULL << 9) 165 #define FSR_OFA (1ULL << 8) 166 #define FSR_UFA (1ULL << 7) 167 #define FSR_DZA (1ULL << 6) 168 #define FSR_NXA (1ULL << 5) 169 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 170 171 #define FSR_NVC (1ULL << 4) 172 #define FSR_OFC (1ULL << 3) 173 #define FSR_UFC (1ULL << 2) 174 #define FSR_DZC (1ULL << 1) 175 #define FSR_NXC (1ULL << 0) 176 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 177 178 #define FSR_FTT2 (1ULL << 16) 179 #define FSR_FTT1 (1ULL << 15) 180 #define FSR_FTT0 (1ULL << 14) 181 //gcc warns about constant overflow for ~FSR_FTT_MASK 182 //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 183 #ifdef TARGET_SPARC64 184 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL 185 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL 186 #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL 187 #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL 188 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL 189 #else 190 #define FSR_FTT_NMASK 0xfffe3fffULL 191 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL 192 #define FSR_LDFSR_OLDMASK 0x000fc000ULL 193 #endif 194 #define FSR_LDFSR_MASK 0xcfc00fffULL 195 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 196 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 197 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 198 #define FSR_FTT_INVAL_FPR (6ULL << 14) 199 200 #define FSR_FCC1_SHIFT 11 201 #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) 202 #define FSR_FCC0_SHIFT 10 203 #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) 204 205 /* MMU */ 206 #define MMU_E (1<<0) 207 #define MMU_NF (1<<1) 208 209 #define PTE_ENTRYTYPE_MASK 3 210 #define PTE_ACCESS_MASK 0x1c 211 #define PTE_ACCESS_SHIFT 2 212 #define PTE_PPN_SHIFT 7 213 #define PTE_ADDR_MASK 0xffffff00 214 215 #define PG_ACCESSED_BIT 5 216 #define PG_MODIFIED_BIT 6 217 #define PG_CACHE_BIT 7 218 219 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 220 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 221 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 222 223 /* 3 <= NWINDOWS <= 32. */ 224 #define MIN_NWINDOWS 3 225 #define MAX_NWINDOWS 32 226 227 #if !defined(TARGET_SPARC64) 228 #define NB_MMU_MODES 3 229 #else 230 #define NB_MMU_MODES 7 231 typedef struct trap_state { 232 uint64_t tpc; 233 uint64_t tnpc; 234 uint64_t tstate; 235 uint32_t tt; 236 } trap_state; 237 #endif 238 #define TARGET_INSN_START_EXTRA_WORDS 1 239 240 typedef struct sparc_def_t { 241 const char *name; 242 target_ulong iu_version; 243 uint32_t fpu_version; 244 uint32_t mmu_version; 245 uint32_t mmu_bm; 246 uint32_t mmu_ctpr_mask; 247 uint32_t mmu_cxr_mask; 248 uint32_t mmu_sfsr_mask; 249 uint32_t mmu_trcr_mask; 250 uint32_t mxcc_version; 251 uint32_t features; 252 uint32_t nwindows; 253 uint32_t maxtl; 254 } sparc_def_t; 255 256 #define CPU_FEATURE_FLOAT (1 << 0) 257 #define CPU_FEATURE_FLOAT128 (1 << 1) 258 #define CPU_FEATURE_SWAP (1 << 2) 259 #define CPU_FEATURE_MUL (1 << 3) 260 #define CPU_FEATURE_DIV (1 << 4) 261 #define CPU_FEATURE_FLUSH (1 << 5) 262 #define CPU_FEATURE_FSQRT (1 << 6) 263 #define CPU_FEATURE_FMUL (1 << 7) 264 #define CPU_FEATURE_VIS1 (1 << 8) 265 #define CPU_FEATURE_VIS2 (1 << 9) 266 #define CPU_FEATURE_FSMULD (1 << 10) 267 #define CPU_FEATURE_HYPV (1 << 11) 268 #define CPU_FEATURE_CMT (1 << 12) 269 #define CPU_FEATURE_GL (1 << 13) 270 #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */ 271 #define CPU_FEATURE_ASR17 (1 << 15) 272 #define CPU_FEATURE_CACHE_CTRL (1 << 16) 273 #define CPU_FEATURE_POWERDOWN (1 << 17) 274 #define CPU_FEATURE_CASA (1 << 18) 275 276 #ifndef TARGET_SPARC64 277 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ 278 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 279 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ 280 CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) 281 #else 282 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ 283 CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 284 CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ 285 CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ 286 CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \ 287 CPU_FEATURE_CASA) 288 enum { 289 mmu_us_12, // Ultrasparc < III (64 entry TLB) 290 mmu_us_3, // Ultrasparc III (512 entry TLB) 291 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 292 mmu_sun4v, // T1, T2 293 }; 294 #endif 295 296 #define TTE_VALID_BIT (1ULL << 63) 297 #define TTE_NFO_BIT (1ULL << 60) 298 #define TTE_USED_BIT (1ULL << 41) 299 #define TTE_LOCKED_BIT (1ULL << 6) 300 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 301 #define TTE_PRIV_BIT (1ULL << 2) 302 #define TTE_W_OK_BIT (1ULL << 1) 303 #define TTE_GLOBAL_BIT (1ULL << 0) 304 305 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 306 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 307 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 308 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 309 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 310 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 311 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 312 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 313 314 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 315 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 316 317 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 318 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 319 320 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 321 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 322 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 323 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 324 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 325 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 326 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 327 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 328 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 329 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 330 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 331 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 332 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 333 334 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 335 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 336 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 337 #define SFSR_CT_SECONDARY (1ULL << 4) 338 #define SFSR_CT_NUCLEUS (2ULL << 4) 339 #define SFSR_CT_NOTRANS (3ULL << 4) 340 #define SFSR_CT_MASK (3ULL << 4) 341 342 /* Leon3 cache control */ 343 344 /* Cache control: emulate the behavior of cache control registers but without 345 any effect on the emulated */ 346 347 #define CACHE_STATE_MASK 0x3 348 #define CACHE_DISABLED 0x0 349 #define CACHE_FROZEN 0x1 350 #define CACHE_ENABLED 0x3 351 352 /* Cache Control register fields */ 353 354 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 355 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 356 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 357 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 358 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 359 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 360 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 361 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 362 363 typedef struct SparcTLBEntry { 364 uint64_t tag; 365 uint64_t tte; 366 } SparcTLBEntry; 367 368 struct CPUTimer 369 { 370 const char *name; 371 uint32_t frequency; 372 uint32_t disabled; 373 uint64_t disabled_mask; 374 uint32_t npt; 375 uint64_t npt_mask; 376 int64_t clock_offset; 377 QEMUTimer *qtimer; 378 }; 379 380 typedef struct CPUTimer CPUTimer; 381 382 typedef struct CPUSPARCState CPUSPARCState; 383 384 struct CPUSPARCState { 385 target_ulong gregs[8]; /* general registers */ 386 target_ulong *regwptr; /* pointer to current register window */ 387 target_ulong pc; /* program counter */ 388 target_ulong npc; /* next program counter */ 389 target_ulong y; /* multiply/divide register */ 390 391 /* emulator internal flags handling */ 392 target_ulong cc_src, cc_src2; 393 target_ulong cc_dst; 394 uint32_t cc_op; 395 396 target_ulong cond; /* conditional branch result (XXX: save it in a 397 temporary register when possible) */ 398 399 uint32_t psr; /* processor state register */ 400 target_ulong fsr; /* FPU state register */ 401 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 402 uint32_t cwp; /* index of current register window (extracted 403 from PSR) */ 404 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 405 uint32_t wim; /* window invalid mask */ 406 #endif 407 target_ulong tbr; /* trap base register */ 408 #if !defined(TARGET_SPARC64) 409 int psrs; /* supervisor mode (extracted from PSR) */ 410 int psrps; /* previous supervisor mode */ 411 int psret; /* enable traps */ 412 #endif 413 uint32_t psrpil; /* interrupt blocking level */ 414 uint32_t pil_in; /* incoming interrupt level bitmap */ 415 #if !defined(TARGET_SPARC64) 416 int psref; /* enable fpu */ 417 #endif 418 int interrupt_index; 419 /* NOTE: we allow 8 more registers to handle wrapping */ 420 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 421 422 /* Fields up to this point are cleared by a CPU reset */ 423 struct {} end_reset_fields; 424 425 CPU_COMMON 426 427 /* Fields from here on are preserved across CPU reset. */ 428 target_ulong version; 429 uint32_t nwindows; 430 431 /* MMU regs */ 432 #if defined(TARGET_SPARC64) 433 uint64_t lsu; 434 #define DMMU_E 0x8 435 #define IMMU_E 0x4 436 //typedef struct SparcMMU 437 union { 438 uint64_t immuregs[16]; 439 struct { 440 uint64_t tsb_tag_target; 441 uint64_t unused_mmu_primary_context; // use DMMU 442 uint64_t unused_mmu_secondary_context; // use DMMU 443 uint64_t sfsr; 444 uint64_t sfar; 445 uint64_t tsb; 446 uint64_t tag_access; 447 } immu; 448 }; 449 union { 450 uint64_t dmmuregs[16]; 451 struct { 452 uint64_t tsb_tag_target; 453 uint64_t mmu_primary_context; 454 uint64_t mmu_secondary_context; 455 uint64_t sfsr; 456 uint64_t sfar; 457 uint64_t tsb; 458 uint64_t tag_access; 459 } dmmu; 460 }; 461 SparcTLBEntry itlb[64]; 462 SparcTLBEntry dtlb[64]; 463 uint32_t mmu_version; 464 #else 465 uint32_t mmuregs[32]; 466 uint64_t mxccdata[4]; 467 uint64_t mxccregs[8]; 468 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 469 uint64_t mmubpaction; 470 uint64_t mmubpregs[4]; 471 uint64_t prom_addr; 472 #endif 473 /* temporary float registers */ 474 float128 qt0, qt1; 475 float_status fp_status; 476 #if defined(TARGET_SPARC64) 477 #define MAXTL_MAX 8 478 #define MAXTL_MASK (MAXTL_MAX - 1) 479 trap_state ts[MAXTL_MAX]; 480 uint32_t xcc; /* Extended integer condition codes */ 481 uint32_t asi; 482 uint32_t pstate; 483 uint32_t tl; 484 uint32_t maxtl; 485 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 486 uint64_t agregs[8]; /* alternate general registers */ 487 uint64_t bgregs[8]; /* backup for normal global registers */ 488 uint64_t igregs[8]; /* interrupt general registers */ 489 uint64_t mgregs[8]; /* mmu general registers */ 490 uint64_t fprs; 491 uint64_t tick_cmpr, stick_cmpr; 492 CPUTimer *tick, *stick; 493 #define TICK_NPT_MASK 0x8000000000000000ULL 494 #define TICK_INT_DIS 0x8000000000000000ULL 495 uint64_t gsr; 496 uint32_t gl; // UA2005 497 /* UA 2005 hyperprivileged registers */ 498 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 499 CPUTimer *hstick; // UA 2005 500 /* Interrupt vector registers */ 501 uint64_t ivec_status; 502 uint64_t ivec_data[3]; 503 uint32_t softint; 504 #define SOFTINT_TIMER 1 505 #define SOFTINT_STIMER (1 << 16) 506 #define SOFTINT_INTRMASK (0xFFFE) 507 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 508 #endif 509 sparc_def_t *def; 510 511 void *irq_manager; 512 void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno); 513 514 /* Leon3 cache control */ 515 uint32_t cache_control; 516 }; 517 518 /** 519 * SPARCCPU: 520 * @env: #CPUSPARCState 521 * 522 * A SPARC CPU. 523 */ 524 struct SPARCCPU { 525 /*< private >*/ 526 CPUState parent_obj; 527 /*< public >*/ 528 529 CPUSPARCState env; 530 }; 531 532 static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) 533 { 534 return container_of(env, SPARCCPU, env); 535 } 536 537 #define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e)) 538 539 #define ENV_OFFSET offsetof(SPARCCPU, env) 540 541 #ifndef CONFIG_USER_ONLY 542 extern const struct VMStateDescription vmstate_sparc_cpu; 543 #endif 544 545 void sparc_cpu_do_interrupt(CPUState *cpu); 546 void sparc_cpu_dump_state(CPUState *cpu, FILE *f, 547 fprintf_function cpu_fprintf, int flags); 548 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 549 int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 550 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 551 void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 552 MMUAccessType access_type, 553 int mmu_idx, 554 uintptr_t retaddr); 555 void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; 556 557 #ifndef NO_CPU_IO_DEFS 558 /* cpu_init.c */ 559 SPARCCPU *cpu_sparc_init(const char *cpu_model); 560 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 561 void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf); 562 /* mmu_helper.c */ 563 int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, 564 int mmu_idx); 565 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 566 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env); 567 568 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 569 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 570 uint8_t *buf, int len, bool is_write); 571 #endif 572 573 574 /* translate.c */ 575 void gen_intermediate_code_init(CPUSPARCState *env); 576 577 /* cpu-exec.c */ 578 579 /* win_helper.c */ 580 target_ulong cpu_get_psr(CPUSPARCState *env1); 581 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 582 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 583 #ifdef TARGET_SPARC64 584 target_ulong cpu_get_ccr(CPUSPARCState *env1); 585 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 586 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 587 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 588 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 589 #endif 590 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 591 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 592 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 593 594 /* int_helper.c */ 595 void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno); 596 597 /* sun4m.c, sun4u.c */ 598 void cpu_check_irqs(CPUSPARCState *env); 599 600 /* leon3.c */ 601 void leon3_irq_ack(void *irq_manager, int intno); 602 603 #if defined (TARGET_SPARC64) 604 605 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 606 { 607 return (x & mask) == (y & mask); 608 } 609 610 #define MMU_CONTEXT_BITS 13 611 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 612 613 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 614 uint64_t context) 615 { 616 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 617 } 618 619 #endif 620 #endif 621 622 /* cpu-exec.c */ 623 #if !defined(CONFIG_USER_ONLY) 624 void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr, 625 bool is_write, bool is_exec, int is_asi, 626 unsigned size); 627 #if defined(TARGET_SPARC64) 628 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 629 int mmu_idx); 630 #endif 631 #endif 632 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); 633 634 #ifndef NO_CPU_IO_DEFS 635 #define cpu_init(cpu_model) CPU(cpu_sparc_init(cpu_model)) 636 #endif 637 638 #define cpu_signal_handler cpu_sparc_signal_handler 639 #define cpu_list sparc_cpu_list 640 641 /* MMU modes definitions */ 642 #if defined (TARGET_SPARC64) 643 #define MMU_USER_IDX 0 644 #define MMU_USER_SECONDARY_IDX 1 645 #define MMU_KERNEL_IDX 2 646 #define MMU_KERNEL_SECONDARY_IDX 3 647 #define MMU_NUCLEUS_IDX 4 648 #define MMU_HYPV_IDX 5 649 #define MMU_PHYS_IDX 6 650 #else 651 #define MMU_USER_IDX 0 652 #define MMU_KERNEL_IDX 1 653 #define MMU_PHYS_IDX 2 654 #endif 655 656 #if defined (TARGET_SPARC64) 657 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 658 { 659 return env1->def->features & CPU_FEATURE_HYPV; 660 } 661 662 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 663 { 664 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 665 } 666 667 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 668 { 669 return env1->pstate & PS_PRIV; 670 } 671 #endif 672 673 static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) 674 { 675 #if defined(CONFIG_USER_ONLY) 676 return MMU_USER_IDX; 677 #elif !defined(TARGET_SPARC64) 678 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ 679 return MMU_PHYS_IDX; 680 } else { 681 return env->psrs; 682 } 683 #else 684 /* IMMU or DMMU disabled. */ 685 if (ifetch 686 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 687 : (env->lsu & DMMU_E) == 0) { 688 return MMU_PHYS_IDX; 689 } else if (env->tl > 0) { 690 return MMU_NUCLEUS_IDX; 691 } else if (cpu_hypervisor_mode(env)) { 692 return MMU_HYPV_IDX; 693 } else if (cpu_supervisor_mode(env)) { 694 return MMU_KERNEL_IDX; 695 } else { 696 return MMU_USER_IDX; 697 } 698 #endif 699 } 700 701 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 702 { 703 #if !defined (TARGET_SPARC64) 704 if (env1->psret != 0) 705 return 1; 706 #else 707 if (env1->pstate & PS_IE) 708 return 1; 709 #endif 710 711 return 0; 712 } 713 714 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 715 { 716 #if !defined(TARGET_SPARC64) 717 /* level 15 is non-maskable on sparc v8 */ 718 return pil == 15 || pil > env1->psrpil; 719 #else 720 return pil > env1->psrpil; 721 #endif 722 } 723 724 #include "exec/cpu-all.h" 725 726 #ifdef TARGET_SPARC64 727 /* sun4u.c */ 728 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 729 uint64_t cpu_tick_get_count(CPUTimer *timer); 730 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 731 trap_state* cpu_tsptr(CPUSPARCState* env); 732 #endif 733 734 #define TB_FLAG_MMU_MASK 7 735 #define TB_FLAG_FPU_ENABLED (1 << 4) 736 #define TB_FLAG_AM_ENABLED (1 << 5) 737 #define TB_FLAG_ASI_SHIFT 24 738 739 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, 740 target_ulong *cs_base, uint32_t *pflags) 741 { 742 uint32_t flags; 743 *pc = env->pc; 744 *cs_base = env->npc; 745 flags = cpu_mmu_index(env, false); 746 #ifdef TARGET_SPARC64 747 if (env->pstate & PS_AM) { 748 flags |= TB_FLAG_AM_ENABLED; 749 } 750 if ((env->def->features & CPU_FEATURE_FLOAT) 751 && (env->pstate & PS_PEF) 752 && (env->fprs & FPRS_FEF)) { 753 flags |= TB_FLAG_FPU_ENABLED; 754 } 755 flags |= env->asi << TB_FLAG_ASI_SHIFT; 756 #else 757 if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) { 758 flags |= TB_FLAG_FPU_ENABLED; 759 } 760 #endif 761 *pflags = flags; 762 } 763 764 static inline bool tb_fpu_enabled(int tb_flags) 765 { 766 #if defined(CONFIG_USER_ONLY) 767 return true; 768 #else 769 return tb_flags & TB_FLAG_FPU_ENABLED; 770 #endif 771 } 772 773 static inline bool tb_am_enabled(int tb_flags) 774 { 775 #ifndef TARGET_SPARC64 776 return false; 777 #else 778 return tb_flags & TB_FLAG_AM_ENABLED; 779 #endif 780 } 781 782 #endif 783