cpu.h (68524e83f8fbe23dca37dc5b847fb558d75c8fab) cpu.h (b597eedcce0de84ff573a6be2cd6a89c7fa0fd8e)
1#ifndef SPARC_CPU_H
2#define SPARC_CPU_H
3
4#include "qemu/bswap.h"
5#include "cpu-qom.h"
6#include "exec/cpu-defs.h"
7#include "qemu/cpu-float.h"
8

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132#define PSR_EF (1<<12)
133#define PSR_PIL 0xf00
134#define PSR_S (1<<7)
135#define PSR_PS (1<<6)
136#define PSR_ET (1<<5)
137#define PSR_CWP 0x1f
138#endif
139
1#ifndef SPARC_CPU_H
2#define SPARC_CPU_H
3
4#include "qemu/bswap.h"
5#include "cpu-qom.h"
6#include "exec/cpu-defs.h"
7#include "qemu/cpu-float.h"
8

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132#define PSR_EF (1<<12)
133#define PSR_PIL 0xf00
134#define PSR_S (1<<7)
135#define PSR_PS (1<<6)
136#define PSR_ET (1<<5)
137#define PSR_CWP 0x1f
138#endif
139
140#define CC_SRC (env->cc_src)
141#define CC_SRC2 (env->cc_src2)
142#define CC_DST (env->cc_dst)
143#define CC_OP (env->cc_op)
144
145/* Even though lazy evaluation of CPU condition codes tends to be less
146 * important on RISC systems where condition codes are only updated
147 * when explicitly requested, SPARC uses it to update 32-bit and 64-bit
148 * condition codes.
149 */
150enum {
151 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
152 CC_OP_FLAGS, /* all cc are back in cc_*_[NZCV] registers */
153 CC_OP_NB,
154};
155
156/* Trap base register */
157#define TBR_BASE_MASK 0xfffff000
158
159#if defined(TARGET_SPARC64)
160#define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */
161#define PS_IG (1<<11) /* v9, zero on UA2007 */
162#define PS_MG (1<<10) /* v9, zero on UA2007 */
163#define PS_CLE (1<<9) /* UA2007 */

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469 * For sparc64, xcc.C is boolean;
470 * icc.C is bit 32 with other bits garbage.
471 */
472 target_ulong icc_C;
473#ifdef TARGET_SPARC64
474 target_ulong xcc_C;
475#endif
476
140/* Trap base register */
141#define TBR_BASE_MASK 0xfffff000
142
143#if defined(TARGET_SPARC64)
144#define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */
145#define PS_IG (1<<11) /* v9, zero on UA2007 */
146#define PS_MG (1<<10) /* v9, zero on UA2007 */
147#define PS_CLE (1<<9) /* UA2007 */

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453 * For sparc64, xcc.C is boolean;
454 * icc.C is bit 32 with other bits garbage.
455 */
456 target_ulong icc_C;
457#ifdef TARGET_SPARC64
458 target_ulong xcc_C;
459#endif
460
477 /* emulator internal flags handling */
478 target_ulong cc_src, cc_src2;
479 target_ulong cc_dst;
480 uint32_t cc_op;
481
482 target_ulong cond; /* conditional branch result (XXX: save it in a
483 temporary register when possible) */
484
485 target_ulong fsr; /* FPU state register */
486 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */
487 uint32_t cwp; /* index of current register window (extracted
488 from PSR) */
489#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)

--- 373 unchanged lines hidden --- 		461 target_ulong cond; /* conditional branch result (XXX: save it in a
462 temporary register when possible) */
463
464 target_ulong fsr; /* FPU state register */
465 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */
466 uint32_t cwp; /* index of current register window (extracted
467 from PSR) */
468#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)

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