1 #ifndef SPARC_CPU_H 2 #define SPARC_CPU_H 3 4 #include "qemu/bswap.h" 5 #include "cpu-qom.h" 6 #include "exec/cpu-defs.h" 7 #include "qemu/cpu-float.h" 8 9 /* 10 * From Oracle SPARC Architecture 2015: 11 * 12 * Compatibility notes: The PSO memory model described in SPARC V8 and 13 * SPARC V9 compatibility architecture specifications was never implemented 14 * in a SPARC V9 implementation and is not included in the Oracle SPARC 15 * Architecture specification. 16 * 17 * The RMO memory model described in the SPARC V9 specification was 18 * implemented in some non-Sun SPARC V9 implementations, but is not 19 * directly supported in Oracle SPARC Architecture 2015 implementations. 20 * 21 * Therefore always use TSO in QEMU. 22 * 23 * D.5 Specification of Partial Store Order (PSO) 24 * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. 25 * 26 * D.6 Specification of Total Store Order (TSO) 27 * ... PSO with the additional requirement that all [stores] are followed 28 * by an implied MEMBAR #StoreStore. 29 */ 30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) 31 32 #if !defined(TARGET_SPARC64) 33 #define TARGET_DPREGS 16 34 #else 35 #define TARGET_DPREGS 32 36 #endif 37 38 /*#define EXCP_INTERRUPT 0x100*/ 39 40 /* Windowed register indexes. */ 41 enum { 42 WREG_O0, 43 WREG_O1, 44 WREG_O2, 45 WREG_O3, 46 WREG_O4, 47 WREG_O5, 48 WREG_O6, 49 WREG_O7, 50 51 WREG_L0, 52 WREG_L1, 53 WREG_L2, 54 WREG_L3, 55 WREG_L4, 56 WREG_L5, 57 WREG_L6, 58 WREG_L7, 59 60 WREG_I0, 61 WREG_I1, 62 WREG_I2, 63 WREG_I3, 64 WREG_I4, 65 WREG_I5, 66 WREG_I6, 67 WREG_I7, 68 69 WREG_SP = WREG_O6, 70 WREG_FP = WREG_I6, 71 }; 72 73 /* trap definitions */ 74 #ifndef TARGET_SPARC64 75 #define TT_TFAULT 0x01 76 #define TT_ILL_INSN 0x02 77 #define TT_PRIV_INSN 0x03 78 #define TT_NFPU_INSN 0x04 79 #define TT_WIN_OVF 0x05 80 #define TT_WIN_UNF 0x06 81 #define TT_UNALIGNED 0x07 82 #define TT_FP_EXCP 0x08 83 #define TT_DFAULT 0x09 84 #define TT_TOVF 0x0a 85 #define TT_EXTINT 0x10 86 #define TT_CODE_ACCESS 0x21 87 #define TT_UNIMP_FLUSH 0x25 88 #define TT_DATA_ACCESS 0x29 89 #define TT_DIV_ZERO 0x2a 90 #define TT_NCP_INSN 0x24 91 #define TT_TRAP 0x80 92 #else 93 #define TT_POWER_ON_RESET 0x01 94 #define TT_TFAULT 0x08 95 #define TT_CODE_ACCESS 0x0a 96 #define TT_ILL_INSN 0x10 97 #define TT_UNIMP_FLUSH TT_ILL_INSN 98 #define TT_PRIV_INSN 0x11 99 #define TT_NFPU_INSN 0x20 100 #define TT_FP_EXCP 0x21 101 #define TT_TOVF 0x23 102 #define TT_CLRWIN 0x24 103 #define TT_DIV_ZERO 0x28 104 #define TT_DFAULT 0x30 105 #define TT_DATA_ACCESS 0x32 106 #define TT_UNALIGNED 0x34 107 #define TT_PRIV_ACT 0x37 108 #define TT_INSN_REAL_TRANSLATION_MISS 0x3e 109 #define TT_DATA_REAL_TRANSLATION_MISS 0x3f 110 #define TT_EXTINT 0x40 111 #define TT_IVEC 0x60 112 #define TT_TMISS 0x64 113 #define TT_DMISS 0x68 114 #define TT_DPROT 0x6c 115 #define TT_SPILL 0x80 116 #define TT_FILL 0xc0 117 #define TT_WOTHER (1 << 5) 118 #define TT_TRAP 0x100 119 #define TT_HTRAP 0x180 120 #endif 121 122 #define PSR_NEG_SHIFT 23 123 #define PSR_NEG (1 << PSR_NEG_SHIFT) 124 #define PSR_ZERO_SHIFT 22 125 #define PSR_ZERO (1 << PSR_ZERO_SHIFT) 126 #define PSR_OVF_SHIFT 21 127 #define PSR_OVF (1 << PSR_OVF_SHIFT) 128 #define PSR_CARRY_SHIFT 20 129 #define PSR_CARRY (1 << PSR_CARRY_SHIFT) 130 #define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY) 131 #if !defined(TARGET_SPARC64) 132 #define PSR_EF (1<<12) 133 #define PSR_PIL 0xf00 134 #define PSR_S (1<<7) 135 #define PSR_PS (1<<6) 136 #define PSR_ET (1<<5) 137 #define PSR_CWP 0x1f 138 #endif 139 140 #define CC_SRC (env->cc_src) 141 #define CC_SRC2 (env->cc_src2) 142 #define CC_DST (env->cc_dst) 143 #define CC_OP (env->cc_op) 144 145 /* Even though lazy evaluation of CPU condition codes tends to be less 146 * important on RISC systems where condition codes are only updated 147 * when explicitly requested, SPARC uses it to update 32-bit and 64-bit 148 * condition codes. 149 */ 150 enum { 151 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ 152 CC_OP_FLAGS, /* all cc are back in cc_*_[NZCV] registers */ 153 CC_OP_NB, 154 }; 155 156 /* Trap base register */ 157 #define TBR_BASE_MASK 0xfffff000 158 159 #if defined(TARGET_SPARC64) 160 #define PS_TCT (1<<12) /* UA2007, impl.dep. trap on control transfer */ 161 #define PS_IG (1<<11) /* v9, zero on UA2007 */ 162 #define PS_MG (1<<10) /* v9, zero on UA2007 */ 163 #define PS_CLE (1<<9) /* UA2007 */ 164 #define PS_TLE (1<<8) /* UA2007 */ 165 #define PS_RMO (1<<7) 166 #define PS_RED (1<<5) /* v9, zero on UA2007 */ 167 #define PS_PEF (1<<4) /* enable fpu */ 168 #define PS_AM (1<<3) /* address mask */ 169 #define PS_PRIV (1<<2) 170 #define PS_IE (1<<1) 171 #define PS_AG (1<<0) /* v9, zero on UA2007 */ 172 173 #define FPRS_DL (1 << 0) 174 #define FPRS_DU (1 << 1) 175 #define FPRS_FEF (1 << 2) 176 177 #define HS_PRIV (1<<2) 178 #endif 179 180 /* Fcc */ 181 #define FSR_RD1 (1ULL << 31) 182 #define FSR_RD0 (1ULL << 30) 183 #define FSR_RD_MASK (FSR_RD1 | FSR_RD0) 184 #define FSR_RD_NEAREST 0 185 #define FSR_RD_ZERO FSR_RD0 186 #define FSR_RD_POS FSR_RD1 187 #define FSR_RD_NEG (FSR_RD1 | FSR_RD0) 188 189 #define FSR_NVM (1ULL << 27) 190 #define FSR_OFM (1ULL << 26) 191 #define FSR_UFM (1ULL << 25) 192 #define FSR_DZM (1ULL << 24) 193 #define FSR_NXM (1ULL << 23) 194 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM) 195 196 #define FSR_NVA (1ULL << 9) 197 #define FSR_OFA (1ULL << 8) 198 #define FSR_UFA (1ULL << 7) 199 #define FSR_DZA (1ULL << 6) 200 #define FSR_NXA (1ULL << 5) 201 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) 202 203 #define FSR_NVC (1ULL << 4) 204 #define FSR_OFC (1ULL << 3) 205 #define FSR_UFC (1ULL << 2) 206 #define FSR_DZC (1ULL << 1) 207 #define FSR_NXC (1ULL << 0) 208 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC) 209 210 #define FSR_FTT2 (1ULL << 16) 211 #define FSR_FTT1 (1ULL << 15) 212 #define FSR_FTT0 (1ULL << 14) 213 #define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0) 214 #ifdef TARGET_SPARC64 215 #define FSR_FTT_NMASK 0xfffffffffffe3fffULL 216 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL 217 #define FSR_LDFSR_OLDMASK 0x0000003f000fc000ULL 218 #define FSR_LDXFSR_MASK 0x0000003fcfc00fffULL 219 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL 220 #else 221 #define FSR_FTT_NMASK 0xfffe3fffULL 222 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL 223 #define FSR_LDFSR_OLDMASK 0x000fc000ULL 224 #endif 225 #define FSR_LDFSR_MASK 0xcfc00fffULL 226 #define FSR_FTT_IEEE_EXCP (1ULL << 14) 227 #define FSR_FTT_UNIMPFPOP (3ULL << 14) 228 #define FSR_FTT_SEQ_ERROR (4ULL << 14) 229 #define FSR_FTT_INVAL_FPR (6ULL << 14) 230 231 #define FSR_FCC1_SHIFT 11 232 #define FSR_FCC1 (1ULL << FSR_FCC1_SHIFT) 233 #define FSR_FCC0_SHIFT 10 234 #define FSR_FCC0 (1ULL << FSR_FCC0_SHIFT) 235 236 /* MMU */ 237 #define MMU_E (1<<0) 238 #define MMU_NF (1<<1) 239 240 #define PTE_ENTRYTYPE_MASK 3 241 #define PTE_ACCESS_MASK 0x1c 242 #define PTE_ACCESS_SHIFT 2 243 #define PTE_PPN_SHIFT 7 244 #define PTE_ADDR_MASK 0xffffff00 245 246 #define PG_ACCESSED_BIT 5 247 #define PG_MODIFIED_BIT 6 248 #define PG_CACHE_BIT 7 249 250 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) 251 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT) 252 #define PG_CACHE_MASK (1 << PG_CACHE_BIT) 253 254 /* 3 <= NWINDOWS <= 32. */ 255 #define MIN_NWINDOWS 3 256 #define MAX_NWINDOWS 32 257 258 #ifdef TARGET_SPARC64 259 typedef struct trap_state { 260 uint64_t tpc; 261 uint64_t tnpc; 262 uint64_t tstate; 263 uint32_t tt; 264 } trap_state; 265 #endif 266 #define TARGET_INSN_START_EXTRA_WORDS 1 267 268 struct sparc_def_t { 269 const char *name; 270 target_ulong iu_version; 271 uint32_t fpu_version; 272 uint32_t mmu_version; 273 uint32_t mmu_bm; 274 uint32_t mmu_ctpr_mask; 275 uint32_t mmu_cxr_mask; 276 uint32_t mmu_sfsr_mask; 277 uint32_t mmu_trcr_mask; 278 uint32_t mxcc_version; 279 uint32_t features; 280 uint32_t nwindows; 281 uint32_t maxtl; 282 }; 283 284 #define FEATURE(X) CPU_FEATURE_BIT_##X, 285 enum { 286 #include "cpu-feature.h.inc" 287 }; 288 289 #undef FEATURE 290 #define FEATURE(X) CPU_FEATURE_##X = 1u << CPU_FEATURE_BIT_##X, 291 292 enum { 293 #include "cpu-feature.h.inc" 294 }; 295 296 #undef FEATURE 297 298 #ifndef TARGET_SPARC64 299 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 300 CPU_FEATURE_FSMULD) 301 #else 302 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ 303 CPU_FEATURE_FSMULD | CPU_FEATURE_CASA | \ 304 CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2) 305 enum { 306 mmu_us_12, // Ultrasparc < III (64 entry TLB) 307 mmu_us_3, // Ultrasparc III (512 entry TLB) 308 mmu_us_4, // Ultrasparc IV (several TLBs, 32 and 256MB pages) 309 mmu_sun4v, // T1, T2 310 }; 311 #endif 312 313 #define TTE_VALID_BIT (1ULL << 63) 314 #define TTE_NFO_BIT (1ULL << 60) 315 #define TTE_IE_BIT (1ULL << 59) 316 #define TTE_USED_BIT (1ULL << 41) 317 #define TTE_LOCKED_BIT (1ULL << 6) 318 #define TTE_SIDEEFFECT_BIT (1ULL << 3) 319 #define TTE_PRIV_BIT (1ULL << 2) 320 #define TTE_W_OK_BIT (1ULL << 1) 321 #define TTE_GLOBAL_BIT (1ULL << 0) 322 323 #define TTE_NFO_BIT_UA2005 (1ULL << 62) 324 #define TTE_USED_BIT_UA2005 (1ULL << 47) 325 #define TTE_LOCKED_BIT_UA2005 (1ULL << 61) 326 #define TTE_SIDEEFFECT_BIT_UA2005 (1ULL << 11) 327 #define TTE_PRIV_BIT_UA2005 (1ULL << 8) 328 #define TTE_W_OK_BIT_UA2005 (1ULL << 6) 329 330 #define TTE_IS_VALID(tte) ((tte) & TTE_VALID_BIT) 331 #define TTE_IS_NFO(tte) ((tte) & TTE_NFO_BIT) 332 #define TTE_IS_IE(tte) ((tte) & TTE_IE_BIT) 333 #define TTE_IS_USED(tte) ((tte) & TTE_USED_BIT) 334 #define TTE_IS_LOCKED(tte) ((tte) & TTE_LOCKED_BIT) 335 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT) 336 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 337 #define TTE_IS_PRIV(tte) ((tte) & TTE_PRIV_BIT) 338 #define TTE_IS_W_OK(tte) ((tte) & TTE_W_OK_BIT) 339 340 #define TTE_IS_NFO_UA2005(tte) ((tte) & TTE_NFO_BIT_UA2005) 341 #define TTE_IS_USED_UA2005(tte) ((tte) & TTE_USED_BIT_UA2005) 342 #define TTE_IS_LOCKED_UA2005(tte) ((tte) & TTE_LOCKED_BIT_UA2005) 343 #define TTE_IS_SIDEEFFECT_UA2005(tte) ((tte) & TTE_SIDEEFFECT_BIT_UA2005) 344 #define TTE_IS_PRIV_UA2005(tte) ((tte) & TTE_PRIV_BIT_UA2005) 345 #define TTE_IS_W_OK_UA2005(tte) ((tte) & TTE_W_OK_BIT_UA2005) 346 347 #define TTE_IS_GLOBAL(tte) ((tte) & TTE_GLOBAL_BIT) 348 349 #define TTE_SET_USED(tte) ((tte) |= TTE_USED_BIT) 350 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT) 351 352 #define TTE_PGSIZE(tte) (((tte) >> 61) & 3ULL) 353 #define TTE_PGSIZE_UA2005(tte) ((tte) & 7ULL) 354 #define TTE_PA(tte) ((tte) & 0x1ffffffe000ULL) 355 356 /* UltraSPARC T1 specific */ 357 #define TLB_UST1_IS_REAL_BIT (1ULL << 9) /* Real translation entry */ 358 #define TLB_UST1_IS_SUN4V_BIT (1ULL << 10) /* sun4u/sun4v TTE format switch */ 359 360 #define SFSR_NF_BIT (1ULL << 24) /* JPS1 NoFault */ 361 #define SFSR_TM_BIT (1ULL << 15) /* JPS1 TLB Miss */ 362 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13) /* USIIi VA out of range (IMMU) */ 363 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12) /* USIIi VA out of range (DMMU) */ 364 #define SFSR_FT_NFO_BIT (1ULL << 11) /* NFO page access */ 365 #define SFSR_FT_ILL_BIT (1ULL << 10) /* illegal LDA/STA ASI */ 366 #define SFSR_FT_ATOMIC_BIT (1ULL << 9) /* atomic op on noncacheable area */ 367 #define SFSR_FT_NF_E_BIT (1ULL << 8) /* NF access on side effect area */ 368 #define SFSR_FT_PRIV_BIT (1ULL << 7) /* privilege violation */ 369 #define SFSR_PR_BIT (1ULL << 3) /* privilege mode */ 370 #define SFSR_WRITE_BIT (1ULL << 2) /* write access mode */ 371 #define SFSR_OW_BIT (1ULL << 1) /* status overwritten */ 372 #define SFSR_VALID_BIT (1ULL << 0) /* status valid */ 373 374 #define SFSR_ASI_SHIFT 16 /* 23:16 ASI value */ 375 #define SFSR_ASI_MASK (0xffULL << SFSR_ASI_SHIFT) 376 #define SFSR_CT_PRIMARY (0ULL << 4) /* 5:4 context type */ 377 #define SFSR_CT_SECONDARY (1ULL << 4) 378 #define SFSR_CT_NUCLEUS (2ULL << 4) 379 #define SFSR_CT_NOTRANS (3ULL << 4) 380 #define SFSR_CT_MASK (3ULL << 4) 381 382 /* Leon3 cache control */ 383 384 /* Cache control: emulate the behavior of cache control registers but without 385 any effect on the emulated */ 386 387 #define CACHE_STATE_MASK 0x3 388 #define CACHE_DISABLED 0x0 389 #define CACHE_FROZEN 0x1 390 #define CACHE_ENABLED 0x3 391 392 /* Cache Control register fields */ 393 394 #define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */ 395 #define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */ 396 #define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */ 397 #define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */ 398 #define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */ 399 #define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */ 400 #define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */ 401 #define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */ 402 403 #define CONVERT_BIT(X, SRC, DST) \ 404 (SRC > DST ? (X) / (SRC / DST) & (DST) : ((X) & SRC) * (DST / SRC)) 405 406 typedef struct SparcTLBEntry { 407 uint64_t tag; 408 uint64_t tte; 409 } SparcTLBEntry; 410 411 struct CPUTimer 412 { 413 const char *name; 414 uint32_t frequency; 415 uint32_t disabled; 416 uint64_t disabled_mask; 417 uint32_t npt; 418 uint64_t npt_mask; 419 int64_t clock_offset; 420 QEMUTimer *qtimer; 421 }; 422 423 typedef struct CPUTimer CPUTimer; 424 425 typedef struct CPUArchState CPUSPARCState; 426 #if defined(TARGET_SPARC64) 427 typedef union { 428 uint64_t mmuregs[16]; 429 struct { 430 uint64_t tsb_tag_target; 431 uint64_t mmu_primary_context; 432 uint64_t mmu_secondary_context; 433 uint64_t sfsr; 434 uint64_t sfar; 435 uint64_t tsb; 436 uint64_t tag_access; 437 uint64_t virtual_watchpoint; 438 uint64_t physical_watchpoint; 439 uint64_t sun4v_ctx_config[2]; 440 uint64_t sun4v_tsb_pointers[4]; 441 }; 442 } SparcV9MMU; 443 #endif 444 struct CPUArchState { 445 target_ulong gregs[8]; /* general registers */ 446 target_ulong *regwptr; /* pointer to current register window */ 447 target_ulong pc; /* program counter */ 448 target_ulong npc; /* next program counter */ 449 target_ulong y; /* multiply/divide register */ 450 451 /* 452 * Bit 31 is for icc, bit 63 for xcc. 453 * Other bits are garbage. 454 */ 455 target_long cc_N; 456 target_long cc_V; 457 458 /* 459 * Z is represented as == 0; any non-zero value is !Z. 460 * For sparc64, the high 32-bits of icc.Z are garbage. 461 */ 462 target_ulong icc_Z; 463 #ifdef TARGET_SPARC64 464 target_ulong xcc_Z; 465 #endif 466 467 /* 468 * For sparc32, icc.C is boolean. 469 * For sparc64, xcc.C is boolean; 470 * icc.C is bit 32 with other bits garbage. 471 */ 472 target_ulong icc_C; 473 #ifdef TARGET_SPARC64 474 target_ulong xcc_C; 475 #endif 476 477 /* emulator internal flags handling */ 478 target_ulong cc_src, cc_src2; 479 target_ulong cc_dst; 480 uint32_t cc_op; 481 482 target_ulong cond; /* conditional branch result (XXX: save it in a 483 temporary register when possible) */ 484 485 target_ulong fsr; /* FPU state register */ 486 CPU_DoubleU fpr[TARGET_DPREGS]; /* floating point registers */ 487 uint32_t cwp; /* index of current register window (extracted 488 from PSR) */ 489 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) 490 uint32_t wim; /* window invalid mask */ 491 #endif 492 target_ulong tbr; /* trap base register */ 493 #if !defined(TARGET_SPARC64) 494 int psrs; /* supervisor mode (extracted from PSR) */ 495 int psrps; /* previous supervisor mode */ 496 int psret; /* enable traps */ 497 #endif 498 uint32_t psrpil; /* interrupt blocking level */ 499 uint32_t pil_in; /* incoming interrupt level bitmap */ 500 #if !defined(TARGET_SPARC64) 501 int psref; /* enable fpu */ 502 #endif 503 int interrupt_index; 504 /* NOTE: we allow 8 more registers to handle wrapping */ 505 target_ulong regbase[MAX_NWINDOWS * 16 + 8]; 506 507 /* Fields up to this point are cleared by a CPU reset */ 508 struct {} end_reset_fields; 509 510 /* Fields from here on are preserved across CPU reset. */ 511 target_ulong version; 512 uint32_t nwindows; 513 514 /* MMU regs */ 515 #if defined(TARGET_SPARC64) 516 uint64_t lsu; 517 #define DMMU_E 0x8 518 #define IMMU_E 0x4 519 SparcV9MMU immu; 520 SparcV9MMU dmmu; 521 SparcTLBEntry itlb[64]; 522 SparcTLBEntry dtlb[64]; 523 uint32_t mmu_version; 524 #else 525 uint32_t mmuregs[32]; 526 uint64_t mxccdata[4]; 527 uint64_t mxccregs[8]; 528 uint32_t mmubpctrv, mmubpctrc, mmubpctrs; 529 uint64_t mmubpaction; 530 uint64_t mmubpregs[4]; 531 uint64_t prom_addr; 532 #endif 533 /* temporary float registers */ 534 float128 qt0, qt1; 535 float_status fp_status; 536 #if defined(TARGET_SPARC64) 537 #define MAXTL_MAX 8 538 #define MAXTL_MASK (MAXTL_MAX - 1) 539 trap_state ts[MAXTL_MAX]; 540 uint32_t asi; 541 uint32_t pstate; 542 uint32_t tl; 543 uint32_t maxtl; 544 uint32_t cansave, canrestore, otherwin, wstate, cleanwin; 545 uint64_t agregs[8]; /* alternate general registers */ 546 uint64_t bgregs[8]; /* backup for normal global registers */ 547 uint64_t igregs[8]; /* interrupt general registers */ 548 uint64_t mgregs[8]; /* mmu general registers */ 549 uint64_t glregs[8 * MAXTL_MAX]; 550 uint32_t fprs; 551 uint64_t tick_cmpr, stick_cmpr; 552 CPUTimer *tick, *stick; 553 #define TICK_NPT_MASK 0x8000000000000000ULL 554 #define TICK_INT_DIS 0x8000000000000000ULL 555 uint64_t gsr; 556 uint32_t gl; // UA2005 557 /* UA 2005 hyperprivileged registers */ 558 uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr; 559 uint64_t scratch[8]; 560 CPUTimer *hstick; // UA 2005 561 /* Interrupt vector registers */ 562 uint64_t ivec_status; 563 uint64_t ivec_data[3]; 564 uint32_t softint; 565 #define SOFTINT_TIMER 1 566 #define SOFTINT_STIMER (1 << 16) 567 #define SOFTINT_INTRMASK (0xFFFE) 568 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) 569 #endif 570 sparc_def_t def; 571 572 void *irq_manager; 573 void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno); 574 575 /* Leon3 cache control */ 576 uint32_t cache_control; 577 }; 578 579 /** 580 * SPARCCPU: 581 * @env: #CPUSPARCState 582 * 583 * A SPARC CPU. 584 */ 585 struct ArchCPU { 586 /*< private >*/ 587 CPUState parent_obj; 588 /*< public >*/ 589 590 CPUSPARCState env; 591 }; 592 593 594 #ifndef CONFIG_USER_ONLY 595 extern const VMStateDescription vmstate_sparc_cpu; 596 597 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 598 #endif 599 600 void sparc_cpu_do_interrupt(CPUState *cpu); 601 int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 602 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 603 G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 604 MMUAccessType access_type, 605 int mmu_idx, 606 uintptr_t retaddr); 607 G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t); 608 609 /* cpu_init.c */ 610 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); 611 void sparc_cpu_list(void); 612 /* mmu_helper.c */ 613 bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 614 MMUAccessType access_type, int mmu_idx, 615 bool probe, uintptr_t retaddr); 616 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); 617 void dump_mmu(CPUSPARCState *env); 618 619 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 620 int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 621 uint8_t *buf, int len, bool is_write); 622 #endif 623 624 625 /* translate.c */ 626 void sparc_tcg_init(void); 627 void sparc_restore_state_to_opc(CPUState *cs, 628 const TranslationBlock *tb, 629 const uint64_t *data); 630 631 /* cpu-exec.c */ 632 633 /* win_helper.c */ 634 target_ulong cpu_get_psr(CPUSPARCState *env1); 635 void cpu_put_psr(CPUSPARCState *env1, target_ulong val); 636 void cpu_put_psr_icc(CPUSPARCState *env1, target_ulong val); 637 void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val); 638 #ifdef TARGET_SPARC64 639 void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate); 640 void cpu_gl_switch_gregs(CPUSPARCState *env, uint32_t new_gl); 641 #endif 642 int cpu_cwp_inc(CPUSPARCState *env1, int cwp); 643 int cpu_cwp_dec(CPUSPARCState *env1, int cwp); 644 void cpu_set_cwp(CPUSPARCState *env1, int new_cwp); 645 646 /* sun4m.c, sun4u.c */ 647 void cpu_check_irqs(CPUSPARCState *env); 648 649 #if defined (TARGET_SPARC64) 650 651 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask) 652 { 653 return (x & mask) == (y & mask); 654 } 655 656 #define MMU_CONTEXT_BITS 13 657 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1) 658 659 static inline int tlb_compare_context(const SparcTLBEntry *tlb, 660 uint64_t context) 661 { 662 return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); 663 } 664 665 #endif 666 667 /* cpu-exec.c */ 668 #if !defined(CONFIG_USER_ONLY) 669 void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 670 vaddr addr, unsigned size, 671 MMUAccessType access_type, 672 int mmu_idx, MemTxAttrs attrs, 673 MemTxResult response, uintptr_t retaddr); 674 #if defined(TARGET_SPARC64) 675 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, 676 int mmu_idx); 677 #endif 678 #endif 679 680 #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU 681 #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX 682 #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU 683 684 #define cpu_list sparc_cpu_list 685 686 /* MMU modes definitions */ 687 #if defined (TARGET_SPARC64) 688 #define MMU_USER_IDX 0 689 #define MMU_USER_SECONDARY_IDX 1 690 #define MMU_KERNEL_IDX 2 691 #define MMU_KERNEL_SECONDARY_IDX 3 692 #define MMU_NUCLEUS_IDX 4 693 #define MMU_PHYS_IDX 5 694 #else 695 #define MMU_USER_IDX 0 696 #define MMU_KERNEL_IDX 1 697 #define MMU_PHYS_IDX 2 698 #endif 699 700 #if defined (TARGET_SPARC64) 701 static inline int cpu_has_hypervisor(CPUSPARCState *env1) 702 { 703 return env1->def.features & CPU_FEATURE_HYPV; 704 } 705 706 static inline int cpu_hypervisor_mode(CPUSPARCState *env1) 707 { 708 return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV); 709 } 710 711 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 712 { 713 return env1->pstate & PS_PRIV; 714 } 715 #else 716 static inline int cpu_supervisor_mode(CPUSPARCState *env1) 717 { 718 return env1->psrs; 719 } 720 #endif 721 722 static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) 723 { 724 #if defined(CONFIG_USER_ONLY) 725 return MMU_USER_IDX; 726 #elif !defined(TARGET_SPARC64) 727 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ 728 return MMU_PHYS_IDX; 729 } else { 730 return env->psrs; 731 } 732 #else 733 /* IMMU or DMMU disabled. */ 734 if (ifetch 735 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 736 : (env->lsu & DMMU_E) == 0) { 737 return MMU_PHYS_IDX; 738 } else if (cpu_hypervisor_mode(env)) { 739 return MMU_PHYS_IDX; 740 } else if (env->tl > 0) { 741 return MMU_NUCLEUS_IDX; 742 } else if (cpu_supervisor_mode(env)) { 743 return MMU_KERNEL_IDX; 744 } else { 745 return MMU_USER_IDX; 746 } 747 #endif 748 } 749 750 static inline int cpu_interrupts_enabled(CPUSPARCState *env1) 751 { 752 #if !defined (TARGET_SPARC64) 753 if (env1->psret != 0) 754 return 1; 755 #else 756 if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) { 757 return 1; 758 } 759 #endif 760 761 return 0; 762 } 763 764 static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil) 765 { 766 #if !defined(TARGET_SPARC64) 767 /* level 15 is non-maskable on sparc v8 */ 768 return pil == 15 || pil > env1->psrpil; 769 #else 770 return pil > env1->psrpil; 771 #endif 772 } 773 774 #include "exec/cpu-all.h" 775 776 #ifdef TARGET_SPARC64 777 /* sun4u.c */ 778 void cpu_tick_set_count(CPUTimer *timer, uint64_t count); 779 uint64_t cpu_tick_get_count(CPUTimer *timer); 780 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); 781 trap_state* cpu_tsptr(CPUSPARCState* env); 782 #endif 783 784 #define TB_FLAG_MMU_MASK 7 785 #define TB_FLAG_FPU_ENABLED (1 << 4) 786 #define TB_FLAG_AM_ENABLED (1 << 5) 787 #define TB_FLAG_SUPER (1 << 6) 788 #define TB_FLAG_HYPER (1 << 7) 789 #define TB_FLAG_ASI_SHIFT 24 790 791 static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, 792 uint64_t *cs_base, uint32_t *pflags) 793 { 794 uint32_t flags; 795 *pc = env->pc; 796 *cs_base = env->npc; 797 flags = cpu_mmu_index(env, false); 798 #ifndef CONFIG_USER_ONLY 799 if (cpu_supervisor_mode(env)) { 800 flags |= TB_FLAG_SUPER; 801 } 802 #endif 803 #ifdef TARGET_SPARC64 804 #ifndef CONFIG_USER_ONLY 805 if (cpu_hypervisor_mode(env)) { 806 flags |= TB_FLAG_HYPER; 807 } 808 #endif 809 if (env->pstate & PS_AM) { 810 flags |= TB_FLAG_AM_ENABLED; 811 } 812 if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { 813 flags |= TB_FLAG_FPU_ENABLED; 814 } 815 flags |= env->asi << TB_FLAG_ASI_SHIFT; 816 #else 817 if (env->psref) { 818 flags |= TB_FLAG_FPU_ENABLED; 819 } 820 #endif 821 *pflags = flags; 822 } 823 824 static inline bool tb_fpu_enabled(int tb_flags) 825 { 826 #if defined(CONFIG_USER_ONLY) 827 return true; 828 #else 829 return tb_flags & TB_FLAG_FPU_ENABLED; 830 #endif 831 } 832 833 static inline bool tb_am_enabled(int tb_flags) 834 { 835 #ifndef TARGET_SPARC64 836 return false; 837 #else 838 return tb_flags & TB_FLAG_AM_ENABLED; 839 #endif 840 } 841 842 #ifdef TARGET_SPARC64 843 /* win_helper.c */ 844 target_ulong cpu_get_ccr(CPUSPARCState *env1); 845 void cpu_put_ccr(CPUSPARCState *env1, target_ulong val); 846 target_ulong cpu_get_cwp64(CPUSPARCState *env1); 847 void cpu_put_cwp64(CPUSPARCState *env1, int cwp); 848 849 static inline uint64_t sparc64_tstate(CPUSPARCState *env) 850 { 851 uint64_t tstate = (cpu_get_ccr(env) << 32) | 852 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | 853 cpu_get_cwp64(env); 854 855 if (env->def.features & CPU_FEATURE_GL) { 856 tstate |= (env->gl & 7ULL) << 40; 857 } 858 return tstate; 859 } 860 #endif 861 862 #endif 863