debug.c (b5f6379d134bd201d52380c73ff73565e6a4321e) debug.c (b6092544fcbe747c005db25c38d8081d281c79ad)
1/*
2 * QEMU RISC-V Native Debug Support
3 *
4 * Copyright (c) 2022 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *

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407 if ((ctrl >> 3) & BIT(env->priv)) {
408 return true;
409 }
410 }
411 }
412
413 return false;
414}
1/*
2 * QEMU RISC-V Native Debug Support
3 *
4 * Copyright (c) 2022 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *

--- 398 unchanged lines hidden (view full) ---

407 if ((ctrl >> 3) & BIT(env->priv)) {
408 return true;
409 }
410 }
411 }
412
413 return false;
414}
415
416void riscv_trigger_init(CPURISCVState *env)
417{
418 target_ulong type2 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
419 int i;
420
421 /* type 2 triggers */
422 for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
423 /*
424 * type = TRIGGER_TYPE_AD_MATCH
425 * dmode = 0 (both debug and M-mode can write tdata)
426 * maskmax = 0 (unimplemented, always 0)
427 * sizehi = 0 (match against any size, RV64 only)
428 * hit = 0 (unimplemented, always 0)
429 * select = 0 (always 0, perform match on address)
430 * timing = 0 (always 0, trigger before instruction)
431 * sizelo = 0 (match against any size)
432 * action = 0 (always 0, raise a breakpoint exception)
433 * chain = 0 (unimplemented, always 0)
434 * match = 0 (always 0, when any compare value equals tdata2)
435 */
436 env->type2_trig[i].mcontrol = type2;
437 env->type2_trig[i].maddress = 0;
438 env->type2_trig[i].bp = NULL;
439 env->type2_trig[i].wp = NULL;
440 }
441}