debug.c (a42bd0016654cafd6ca8ca4dbb82fc921ca19ae4) debug.c (9d5a84db91f12bd843206a57e0cde01e6a9d488d)
1/*
2 * QEMU RISC-V Native Debug Support
3 *
4 * Copyright (c) 2022 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *

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90
91static inline target_ulong get_trigger_type(CPURISCVState *env,
92 target_ulong trigger_index)
93{
94 target_ulong tdata1 = env->type2_trig[trigger_index].mcontrol;
95 return extract_trigger_type(env, tdata1);
96}
97
1/*
2 * QEMU RISC-V Native Debug Support
3 *
4 * Copyright (c) 2022 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *

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90
91static inline target_ulong get_trigger_type(CPURISCVState *env,
92 target_ulong trigger_index)
93{
94 target_ulong tdata1 = env->type2_trig[trigger_index].mcontrol;
95 return extract_trigger_type(env, tdata1);
96}
97
98static inline target_ulong trigger_type(CPURISCVState *env,
99 trigger_type_t type)
98static inline target_ulong build_tdata1(CPURISCVState *env,
99 trigger_type_t type,
100 bool dmode, target_ulong data)
100{
101 target_ulong tdata1;
102
103 switch (riscv_cpu_mxl(env)) {
104 case MXL_RV32:
101{
102 target_ulong tdata1;
103
104 switch (riscv_cpu_mxl(env)) {
105 case MXL_RV32:
105 tdata1 = RV32_TYPE(type);
106 tdata1 = RV32_TYPE(type) |
107 (dmode ? RV32_DMODE : 0) |
108 (data & RV32_DATA_MASK);
106 break;
107 case MXL_RV64:
108 case MXL_RV128:
109 break;
110 case MXL_RV64:
111 case MXL_RV128:
109 tdata1 = RV64_TYPE(type);
112 tdata1 = RV64_TYPE(type) |
113 (dmode ? RV64_DMODE : 0) |
114 (data & RV64_DATA_MASK);
110 break;
111 default:
112 g_assert_not_reached();
113 }
114
115 return tdata1;
116}
117

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490 }
491 }
492
493 return false;
494}
495
496void riscv_trigger_init(CPURISCVState *env)
497{
115 break;
116 default:
117 g_assert_not_reached();
118 }
119
120 return tdata1;
121}
122

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495 }
496 }
497
498 return false;
499}
500
501void riscv_trigger_init(CPURISCVState *env)
502{
498 target_ulong tdata1 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
503 target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
499 int i;
500
501 /* init to type 2 triggers */
502 for (i = 0; i < RV_MAX_TRIGGERS; i++) {
503 /*
504 * type = TRIGGER_TYPE_AD_MATCH
505 * dmode = 0 (both debug and M-mode can write tdata)
506 * maskmax = 0 (unimplemented, always 0)

--- 15 unchanged lines hidden --- 		504 int i;
505
506 /* init to type 2 triggers */
507 for (i = 0; i < RV_MAX_TRIGGERS; i++) {
508 /*
509 * type = TRIGGER_TYPE_AD_MATCH
510 * dmode = 0 (both debug and M-mode can write tdata)
511 * maskmax = 0 (unimplemented, always 0)

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