debug.c (6ea8d3fc40a8db8d22d00255cea9f9f8c927d643) debug.c (31b9798d824512b7daf868cc8581f9a97a9d13a8)
1/*
2 * QEMU RISC-V Native Debug Support
3 *
4 * Copyright (c) 2022 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *

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32
33/*
34 * The following M-mode trigger CSRs are implemented:
35 *
36 * - tselect
37 * - tdata1
38 * - tdata2
39 * - tdata3
1/*
2 * QEMU RISC-V Native Debug Support
3 *
4 * Copyright (c) 2022 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *

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32
33/*
34 * The following M-mode trigger CSRs are implemented:
35 *
36 * - tselect
37 * - tdata1
38 * - tdata2
39 * - tdata3
40 * - tinfo
40 *
41 *
41 * We don't support writable 'type' field in the tdata1 register, so there is
42 * no need to implement the "tinfo" CSR.
43 *
44 * The following triggers are implemented:
45 *
46 * Index | Type | tdata mapping | Description
47 * ------+------+------------------------+------------
48 * 0 | 2 | tdata1, tdata2 | Address / Data Match
49 * 1 | 2 | tdata1, tdata2 | Address / Data Match
50 */
51

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367 qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
368 trigger_type);
369 break;
370 default:
371 g_assert_not_reached();
372 }
373}
374
42 * The following triggers are implemented:
43 *
44 * Index | Type | tdata mapping | Description
45 * ------+------+------------------------+------------
46 * 0 | 2 | tdata1, tdata2 | Address / Data Match
47 * 1 | 2 | tdata1, tdata2 | Address / Data Match
48 */
49

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365 qemu_log_mask(LOG_GUEST_ERROR, "trigger type: %d does not exit\n",
366 trigger_type);
367 break;
368 default:
369 g_assert_not_reached();
370 }
371}
372
373target_ulong tinfo_csr_read(CPURISCVState *env)
374{
375 /* assume all triggers support the same types of triggers */
376 return BIT(TRIGGER_TYPE_AD_MATCH);
377}
378
375void riscv_cpu_debug_excp_handler(CPUState *cs)
376{
377 RISCVCPU *cpu = RISCV_CPU(cs);
378 CPURISCVState *env = &cpu->env;
379
380 if (cs->watchpoint_hit) {
381 if (cs->watchpoint_hit->flags & BP_CPU) {
382 cs->watchpoint_hit = NULL;

--- 114 unchanged lines hidden --- 		379void riscv_cpu_debug_excp_handler(CPUState *cs)
380{
381 RISCVCPU *cpu = RISCV_CPU(cs);
382 CPURISCVState *env = &cpu->env;
383
384 if (cs->watchpoint_hit) {
385 if (cs->watchpoint_hit->flags & BP_CPU) {
386 cs->watchpoint_hit = NULL;

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