cpu.h (53677acf25afa8e529d7f81a6ae9a03d15c72713) cpu.h (e91a7227cb802ea62ffa14707ebc2f588b01213d)
1/*
2 * QEMU RISC-V CPU
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,

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20#ifndef RISCV_CPU_H
21#define RISCV_CPU_H
22
23#include "hw/core/cpu.h"
24#include "hw/registerfields.h"
25#include "exec/cpu-defs.h"
26#include "fpu/softfloat-types.h"
27#include "qom/object.h"
1/*
2 * QEMU RISC-V CPU
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,

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20#ifndef RISCV_CPU_H
21#define RISCV_CPU_H
22
23#include "hw/core/cpu.h"
24#include "hw/registerfields.h"
25#include "exec/cpu-defs.h"
26#include "fpu/softfloat-types.h"
27#include "qom/object.h"
28#include "cpu_bits.h"
28
29#define TCG_GUEST_DEFAULT_MO 0
30
31#define TYPE_RISCV_CPU "riscv-cpu"
32
33#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
34#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
35#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU

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46#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
47
48#if defined(TARGET_RISCV32)
49# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
50#elif defined(TARGET_RISCV64)
51# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
52#endif
53
29
30#define TCG_GUEST_DEFAULT_MO 0
31
32#define TYPE_RISCV_CPU "riscv-cpu"
33
34#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
35#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
36#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU

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47#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
48
49#if defined(TARGET_RISCV32)
50# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
51#elif defined(TARGET_RISCV64)
52# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
53#endif
54
54#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
55#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
56
57#define RV(x) ((target_ulong)1 << (x - 'A'))
58
59#define RVI RV('I')
60#define RVE RV('E') /* E and I are mutually exclusive */
61#define RVM RV('M')
62#define RVA RV('A')
63#define RVF RV('F')
64#define RVD RV('D')

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128 target_ulong frm;
129
130 target_ulong badaddr;
131 target_ulong guest_phys_fault_addr;
132
133 target_ulong priv_ver;
134 target_ulong bext_ver;
135 target_ulong vext_ver;
55#define RV(x) ((target_ulong)1 << (x - 'A'))
56
57#define RVI RV('I')
58#define RVE RV('E') /* E and I are mutually exclusive */
59#define RVM RV('M')
60#define RVA RV('A')
61#define RVF RV('F')
62#define RVD RV('D')

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126 target_ulong frm;
127
128 target_ulong badaddr;
129 target_ulong guest_phys_fault_addr;
130
131 target_ulong priv_ver;
132 target_ulong bext_ver;
133 target_ulong vext_ver;
136 target_ulong misa;
137 target_ulong misa_mask;
138
134
135 /* RISCVMXL, but uint32_t for vmstate migration */
136 uint32_t misa_mxl; /* current mxl */
137 uint32_t misa_mxl_max; /* max mxl for this cpu */
138 uint32_t misa_ext; /* current extensions */
139 uint32_t misa_ext_mask; /* max ext for this cpu */
140
139 uint32_t features;
140
141#ifdef CONFIG_USER_ONLY
142 uint32_t elf_flags;
143#endif
144
145#ifndef CONFIG_USER_ONLY
146 target_ulong priv;

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308 bool pmp;
309 bool epmp;
310 uint64_t resetvec;
311 } cfg;
312};
313
314static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
315{
141 uint32_t features;
142
143#ifdef CONFIG_USER_ONLY
144 uint32_t elf_flags;
145#endif
146
147#ifndef CONFIG_USER_ONLY
148 target_ulong priv;

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310 bool pmp;
311 bool epmp;
312 uint64_t resetvec;
313 } cfg;
314};
315
316static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
317{
316 return (env->misa & ext) != 0;
318 return (env->misa_ext & ext) != 0;
317}
318
319static inline bool riscv_feature(CPURISCVState *env, int feature)
320{
321 return env->features & (1ULL << feature);
322}
323
324#include "cpu_user.h"
319}
320
321static inline bool riscv_feature(CPURISCVState *env, int feature)
322{
323 return env->features & (1ULL << feature);
324}
325
326#include "cpu_user.h"
325#include "cpu_bits.h"
326
327extern const char * const riscv_int_regnames[];
328extern const char * const riscv_fpr_regnames[];
329
330const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
331void riscv_cpu_do_interrupt(CPUState *cpu);
332int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
333 int cpuid, void *opaque);

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328extern const char * const riscv_int_regnames[];
329extern const char * const riscv_fpr_regnames[];
330
331const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
332void riscv_cpu_do_interrupt(CPUState *cpu);
333int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
334 int cpuid, void *opaque);

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