cpu.c (5683750909fb407261b5ad00fed4ad9460ab6845) cpu.c (8fc5239e1f8df617147dfe9761dd78291fea78d7)
1/*
2 * QEMU MicroBlaze CPU
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
8 *

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152
153 env->pvr.regs[0] = PVR0_USE_EXC_MASK \
154 | PVR0_USE_ICACHE_MASK \
155 | PVR0_USE_DCACHE_MASK;
156 env->pvr.regs[2] = PVR2_D_OPB_MASK \
157 | PVR2_D_LMB_MASK \
158 | PVR2_I_OPB_MASK \
159 | PVR2_I_LMB_MASK \
1/*
2 * QEMU MicroBlaze CPU
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
8 *

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152
153 env->pvr.regs[0] = PVR0_USE_EXC_MASK \
154 | PVR0_USE_ICACHE_MASK \
155 | PVR0_USE_DCACHE_MASK;
156 env->pvr.regs[2] = PVR2_D_OPB_MASK \
157 | PVR2_D_LMB_MASK \
158 | PVR2_I_OPB_MASK \
159 | PVR2_I_LMB_MASK \
160 | PVR2_USE_PCMP_INSTR \
161 | PVR2_FPU_EXC_MASK \
162 | 0;
163
164 for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
165 if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
166 version_code = mb_cpu_lookup[i].version_id;
167 break;
168 }

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183 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
184
185 env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
186 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
187 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
188 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
189 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
190 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
160 | PVR2_FPU_EXC_MASK \
161 | 0;
162
163 for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
164 if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
165 version_code = mb_cpu_lookup[i].version_id;
166 break;
167 }

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182 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
183
184 env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
185 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
186 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
187 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
188 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
189 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
191 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0);
190 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
191 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0);
192
193 env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
194 PVR5_DCACHE_WRITEBACK_MASK : 0;
195
196 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
197 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
198
199 mcc->parent_realize(dev, errp);

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237 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
238 /* If use-hw-mul > 0 - Multiplier is enabled
239 * If use-hw-mul = 2 - 64-bit multiplier is enabled
240 */
241 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
242 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
243 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
244 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
192
193 env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
194 PVR5_DCACHE_WRITEBACK_MASK : 0;
195
196 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
197 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
198
199 mcc->parent_realize(dev, errp);

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237 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
238 /* If use-hw-mul > 0 - Multiplier is enabled
239 * If use-hw-mul = 2 - 64-bit multiplier is enabled
240 */
241 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
242 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
243 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
244 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
245 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
245 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
246 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
247 false),
248 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
249 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
250 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
251 DEFINE_PROP_END_OF_LIST(),
252};

--- 48 unchanged lines hidden --- 		246 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
247 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
248 false),
249 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
250 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
251 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
252 DEFINE_PROP_END_OF_LIST(),
253};

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