1 /* 2 * QEMU MicroBlaze CPU 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * Copyright (c) 2012 SUSE LINUX Products GmbH 7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "qemu-common.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "exec/exec-all.h" 31 32 static const struct { 33 const char *name; 34 uint8_t version_id; 35 } mb_cpu_lookup[] = { 36 /* These key value are as per MBV field in PVR0 */ 37 {"5.00.a", 0x01}, 38 {"5.00.b", 0x02}, 39 {"5.00.c", 0x03}, 40 {"6.00.a", 0x04}, 41 {"6.00.b", 0x06}, 42 {"7.00.a", 0x05}, 43 {"7.00.b", 0x07}, 44 {"7.10.a", 0x08}, 45 {"7.10.b", 0x09}, 46 {"7.10.c", 0x0a}, 47 {"7.10.d", 0x0b}, 48 {"7.20.a", 0x0c}, 49 {"7.20.b", 0x0d}, 50 {"7.20.c", 0x0e}, 51 {"7.20.d", 0x0f}, 52 {"7.30.a", 0x10}, 53 {"7.30.b", 0x11}, 54 {"8.00.a", 0x12}, 55 {"8.00.b", 0x13}, 56 {"8.10.a", 0x14}, 57 {"8.20.a", 0x15}, 58 {"8.20.b", 0x16}, 59 {"8.30.a", 0x17}, 60 {"8.40.a", 0x18}, 61 {"8.40.b", 0x19}, 62 {"8.50.a", 0x1A}, 63 {"9.0", 0x1B}, 64 {"9.1", 0x1D}, 65 {"9.2", 0x1F}, 66 {"9.3", 0x20}, 67 {"9.4", 0x21}, 68 {"9.5", 0x22}, 69 {"9.6", 0x23}, 70 {NULL, 0}, 71 }; 72 73 static void mb_cpu_set_pc(CPUState *cs, vaddr value) 74 { 75 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 76 77 cpu->env.sregs[SR_PC] = value; 78 } 79 80 static bool mb_cpu_has_work(CPUState *cs) 81 { 82 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 83 } 84 85 #ifndef CONFIG_USER_ONLY 86 static void microblaze_cpu_set_irq(void *opaque, int irq, int level) 87 { 88 MicroBlazeCPU *cpu = opaque; 89 CPUState *cs = CPU(cpu); 90 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; 91 92 if (level) { 93 cpu_interrupt(cs, type); 94 } else { 95 cpu_reset_interrupt(cs, type); 96 } 97 } 98 #endif 99 100 /* CPUClass::reset() */ 101 static void mb_cpu_reset(CPUState *s) 102 { 103 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); 104 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); 105 CPUMBState *env = &cpu->env; 106 107 mcc->parent_reset(s); 108 109 memset(env, 0, offsetof(CPUMBState, end_reset_fields)); 110 env->res_addr = RES_ADDR_NONE; 111 112 /* Disable stack protector. */ 113 env->shr = ~0; 114 115 env->sregs[SR_PC] = cpu->cfg.base_vectors; 116 117 #if defined(CONFIG_USER_ONLY) 118 /* start in user mode with interrupts enabled. */ 119 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; 120 #else 121 env->sregs[SR_MSR] = 0; 122 mmu_init(&env->mmu); 123 env->mmu.c_mmu = 3; 124 env->mmu.c_mmu_tlb_access = 3; 125 env->mmu.c_mmu_zones = 16; 126 #endif 127 } 128 129 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) 130 { 131 info->mach = bfd_arch_microblaze; 132 info->print_insn = print_insn_microblaze; 133 } 134 135 static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 136 { 137 CPUState *cs = CPU(dev); 138 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); 139 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 140 CPUMBState *env = &cpu->env; 141 uint8_t version_code = 0; 142 int i = 0; 143 Error *local_err = NULL; 144 145 cpu_exec_realizefn(cs, &local_err); 146 if (local_err != NULL) { 147 error_propagate(errp, local_err); 148 return; 149 } 150 151 qemu_init_vcpu(cs); 152 153 env->pvr.regs[0] = PVR0_USE_EXC_MASK \ 154 | PVR0_USE_ICACHE_MASK \ 155 | PVR0_USE_DCACHE_MASK; 156 env->pvr.regs[2] = PVR2_D_OPB_MASK \ 157 | PVR2_D_LMB_MASK \ 158 | PVR2_I_OPB_MASK \ 159 | PVR2_I_LMB_MASK \ 160 | PVR2_FPU_EXC_MASK \ 161 | 0; 162 163 for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) { 164 if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) { 165 version_code = mb_cpu_lookup[i].version_id; 166 break; 167 } 168 } 169 170 if (!version_code) { 171 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); 172 } 173 174 env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | 175 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | 176 (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | 177 (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | 178 (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | 179 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | 180 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | 181 (version_code << PVR0_VERSION_SHIFT) | 182 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); 183 184 env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | 185 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | 186 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | 187 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | 188 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | 189 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | 190 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | 191 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0); 192 193 env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? 194 PVR5_DCACHE_WRITEBACK_MASK : 0; 195 196 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ 197 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); 198 199 mcc->parent_realize(dev, errp); 200 } 201 202 static void mb_cpu_initfn(Object *obj) 203 { 204 CPUState *cs = CPU(obj); 205 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); 206 CPUMBState *env = &cpu->env; 207 static bool tcg_initialized; 208 209 cs->env_ptr = env; 210 211 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); 212 213 #ifndef CONFIG_USER_ONLY 214 /* Inbound IRQ and FIR lines */ 215 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); 216 #endif 217 218 if (tcg_enabled() && !tcg_initialized) { 219 tcg_initialized = true; 220 mb_tcg_init(); 221 } 222 } 223 224 static const VMStateDescription vmstate_mb_cpu = { 225 .name = "cpu", 226 .unmigratable = 1, 227 }; 228 229 static Property mb_properties[] = { 230 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), 231 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, 232 false), 233 /* If use-fpu > 0 - FPU is enabled 234 * If use-fpu = 2 - Floating point conversion and square root instructions 235 * are enabled 236 */ 237 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), 238 /* If use-hw-mul > 0 - Multiplier is enabled 239 * If use-hw-mul = 2 - 64-bit multiplier is enabled 240 */ 241 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), 242 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), 243 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), 244 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), 245 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), 246 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), 247 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, 248 false), 249 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), 250 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), 251 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), 252 DEFINE_PROP_END_OF_LIST(), 253 }; 254 255 static void mb_cpu_class_init(ObjectClass *oc, void *data) 256 { 257 DeviceClass *dc = DEVICE_CLASS(oc); 258 CPUClass *cc = CPU_CLASS(oc); 259 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); 260 261 mcc->parent_realize = dc->realize; 262 dc->realize = mb_cpu_realizefn; 263 264 mcc->parent_reset = cc->reset; 265 cc->reset = mb_cpu_reset; 266 267 cc->has_work = mb_cpu_has_work; 268 cc->do_interrupt = mb_cpu_do_interrupt; 269 cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; 270 cc->dump_state = mb_cpu_dump_state; 271 cc->set_pc = mb_cpu_set_pc; 272 cc->gdb_read_register = mb_cpu_gdb_read_register; 273 cc->gdb_write_register = mb_cpu_gdb_write_register; 274 #ifdef CONFIG_USER_ONLY 275 cc->handle_mmu_fault = mb_cpu_handle_mmu_fault; 276 #else 277 cc->do_unassigned_access = mb_cpu_unassigned_access; 278 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; 279 #endif 280 dc->vmsd = &vmstate_mb_cpu; 281 dc->props = mb_properties; 282 cc->gdb_num_core_regs = 32 + 5; 283 284 cc->disas_set_info = mb_disas_set_info; 285 } 286 287 static const TypeInfo mb_cpu_type_info = { 288 .name = TYPE_MICROBLAZE_CPU, 289 .parent = TYPE_CPU, 290 .instance_size = sizeof(MicroBlazeCPU), 291 .instance_init = mb_cpu_initfn, 292 .class_size = sizeof(MicroBlazeCPUClass), 293 .class_init = mb_cpu_class_init, 294 }; 295 296 static void mb_cpu_register_types(void) 297 { 298 type_register_static(&mb_cpu_type_info); 299 } 300 301 type_init(mb_cpu_register_types) 302