cpu.c (910e4f24975f53645d308aa6c895f4599dd47c43) cpu.c (761c46425e2d2a7a65cbbd1ee65f0abce769618c)
1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

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486 memset(env->pmsav7.drbar, 0,
487 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
488 memset(env->pmsav7.drsr, 0,
489 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
490 memset(env->pmsav7.dracr, 0,
491 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
492 }
493 }
1/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2

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486 memset(env->pmsav7.drbar, 0,
487 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
488 memset(env->pmsav7.drsr, 0,
489 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
490 memset(env->pmsav7.dracr, 0,
491 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
492 }
493 }
494
495 if (cpu->pmsav8r_hdregion > 0) {
496 memset(env->pmsav8.hprbar, 0,
497 sizeof(*env->pmsav8.hprbar) * cpu->pmsav8r_hdregion);
498 memset(env->pmsav8.hprlar, 0,
499 sizeof(*env->pmsav8.hprlar) * cpu->pmsav8r_hdregion);
500 }
501
494 env->pmsav7.rnr[M_REG_NS] = 0;
495 env->pmsav7.rnr[M_REG_S] = 0;
496 env->pmsav8.mair0[M_REG_NS] = 0;
497 env->pmsav8.mair0[M_REG_S] = 0;
498 env->pmsav8.mair1[M_REG_NS] = 0;
499 env->pmsav8.mair1[M_REG_S] = 0;
500 }
501

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1997 */
1998 cpu->isar.id_aa64dfr0 =
1999 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
2000 }
2001
2002 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
2003 * to false or by setting pmsav7-dregion to 0.
2004 */
502 env->pmsav7.rnr[M_REG_NS] = 0;
503 env->pmsav7.rnr[M_REG_S] = 0;
504 env->pmsav8.mair0[M_REG_NS] = 0;
505 env->pmsav8.mair0[M_REG_S] = 0;
506 env->pmsav8.mair1[M_REG_NS] = 0;
507 env->pmsav8.mair1[M_REG_S] = 0;
508 }
509

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2005 */
2006 cpu->isar.id_aa64dfr0 =
2007 FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
2008 }
2009
2010 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
2011 * to false or by setting pmsav7-dregion to 0.
2012 */
2005 if (!cpu->has_mpu) {
2013 if (!cpu->has_mpu || cpu->pmsav7_dregion == 0) {
2014 cpu->has_mpu = false;
2006 cpu->pmsav7_dregion = 0;
2015 cpu->pmsav7_dregion = 0;
2016 cpu->pmsav8r_hdregion = 0;
2007 }
2017 }
2008 if (cpu->pmsav7_dregion == 0) {
2009 cpu->has_mpu = false;
2010 }
2011
2012 if (arm_feature(env, ARM_FEATURE_PMSA) &&
2013 arm_feature(env, ARM_FEATURE_V7)) {
2014 uint32_t nr = cpu->pmsav7_dregion;
2015
2016 if (nr > 0xff) {
2017 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
2018 return;

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2028 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
2029 }
2030 } else {
2031 env->pmsav7.drbar = g_new0(uint32_t, nr);
2032 env->pmsav7.drsr = g_new0(uint32_t, nr);
2033 env->pmsav7.dracr = g_new0(uint32_t, nr);
2034 }
2035 }
2018
2019 if (arm_feature(env, ARM_FEATURE_PMSA) &&
2020 arm_feature(env, ARM_FEATURE_V7)) {
2021 uint32_t nr = cpu->pmsav7_dregion;
2022
2023 if (nr > 0xff) {
2024 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
2025 return;

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2035 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
2036 }
2037 } else {
2038 env->pmsav7.drbar = g_new0(uint32_t, nr);
2039 env->pmsav7.drsr = g_new0(uint32_t, nr);
2040 env->pmsav7.dracr = g_new0(uint32_t, nr);
2041 }
2042 }
2043
2044 if (cpu->pmsav8r_hdregion > 0xff) {
2045 error_setg(errp, "PMSAv8 MPU EL2 #regions invalid %" PRIu32,
2046 cpu->pmsav8r_hdregion);
2047 return;
2048 }
2049
2050 if (cpu->pmsav8r_hdregion) {
2051 env->pmsav8.hprbar = g_new0(uint32_t,
2052 cpu->pmsav8r_hdregion);
2053 env->pmsav8.hprlar = g_new0(uint32_t,
2054 cpu->pmsav8r_hdregion);
2055 }
2036 }
2037
2038 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2039 uint32_t nr = cpu->sau_sregion;
2040
2041 if (nr > 0xff) {
2042 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
2043 return;

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2057
2058 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
2059 uint32_t nr = cpu->sau_sregion;
2060
2061 if (nr > 0xff) {
2062 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
2063 return;

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